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參數(shù)資料
| 型號： | EDS1232AABB-75L |
| 英文描述： | SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC |
| 中文描述： | 內存| 4X1MX32 |的CMOS | BGA封裝| 90PIN |塑料 |
| 文件頁數(shù)： | 32/55頁 |
| 文件大?。?/td> | 570K |
| 代理商： | EDS1232AABB-75L |
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EDS1232AABB, EDS1232AATA
Data Sheet E0205E30 (Ver. 3.0)
38
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-
precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
DQ (output)
DQ (input)
CL = 2
CL = 3
READA
WRIT
in B0
in B1
in B2
in B3
BL = 4
bank0
ReadA
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
DQM
High-Z
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
CLK
Command
BS
DQ (output)
DQ (input)
WRITA
READ
out B0
out B1
out B2
out B3
CL = 3
BL = 4
bank0
WriteA
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by "
".
DQM
in A0
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
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| EDS1232AABB-75L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
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| EDS1232AASE-75-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
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