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| 型號： | DS31412N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 61/89頁 |
| 文件大小： | 0K |
| 描述： | IC 12CH DS3/3 FRAMER 349-BGA |
| 標準包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 960mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應商設備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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Table 7-I. FEAC Register Map
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
60h
N/A
RFR
TFS1
TFS0
61h
N/A
RFFE
RFI
RFCD
TFI
62h
N/A
RFFOL
RFFNL
RFIL
RFCDL
TFIL
63h
N/A
RFFOIE
RFFNIE
RFIIE
RFCDIE
TFIIE
64h
N/A
TFCA5
TFCA4
TFCA3
TFCA2
TFCA1
TFCA0
65h
N/A
TFCB5
TFCB4
TFCB3
TFCB2
TFCB1
TFCB0
66h
N/A
RFF5
RFF4
RFF3
RFF2
RFF1
RFF0
Register Name:
FCR
Register Description:
FEAC Control Register
Register Address:
60h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RFR
TFS1
TFS0
Default
—
0
Bits 0, 1: Transmit FEAC Codeword Select Bits 0 and 1 (TFS[1:0]). These two bits control which of the two
available codewords are to be generated. Both TFS0 and TFS1 are edge-triggered; a change from 00 to any other
value starts the desired FEAC transmission. Actions 01 and 10 continue to completion even if TFS is subsequently
written with 00. Action 11 transmits at least 10 codewords before being terminated by TFS = 00. To initiate a new
action, the host must select the idle state (TFS = 00) before selecting the new action.
TFS[1:0]
ACTION
00
Idle state; do not generate a FEAC codeword (send all ones)
01
Send codeword A 10 times followed by all ones
10
Send codeword A 10 times followed codeword B 10 times followed by all ones
11
Send codeword A continuously (sent at least 10 times)
Bit 2: Receive FEAC Reset (RFR). A 0-to-1 transition resets the FEAC receiver and flushes the receive FEAC
FIFO. This bit must be cleared before generating a subsequent reset.
Register Name:
FSR
Register Description:
FEAC Status Register
Register Address:
61h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RFI
RFCD
TFI
Default
—
Bit 0: Transmit FEAC Idle (TFI). This real-time status bit is set when the FEAC transmitter is sending the all-ones
idle code. It is cleared when the FEAC transmitter is sending a FEAC codeword.
Bit 1: Receive FEAC Codeword Detected (RFCD). This real-time status bit is set each time the FEAC receiver
has detected and validated a new FEAC codeword. It is cleared when the validated codeword is no longer present
on the FEAC channel.
Bit 2: Receive FEAC Idle (RFI). This real-time status bit is set when the FEAC controller has detected 16
consecutive 1s. It is cleared when the FEAC receiver has detected and validated a new FEAC codeword.
Bit 3: Receive FEAC FIFO Empty (RFFE). This real-time status bit is set when the receive FEAC FIFO is empty,
and thus RFF[5:0] contains no valid information. It is cleared when the receive FIFO contains one or more
codewords.
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