參數(shù)資料
型號(hào)： DS31412N
廠商： Maxim Integrated Products
文件頁數(shù)： 6/89頁
文件大?。?/td> 0K
描述： IC 12CH DS3/3 FRAMER 349-BGA
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 960mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
14 of 89
5.5 CPU Bus Interface Pins
NAME
TYPE
FUNCTION
MOT
I
Motorola Bus Mode Select. This pin controls whether the CPU bus operates in Intel mode or in Motorola
mode.
0 = CPU bus is in Intel mode
1 = CPU bus is in Motorola mode
D[7:0]
I/O
CPU Bus Data. The host processor accesses the devices’ internal registers through this bus. These pins
are outputs during reads and inputs otherwise. D7 is the MSB; D0 is the LSB.
A[11:0]
I
CPU Bus Address. The host processor specifies the address of the internal register to be accessed by
this bus. Pins A[11:8] specify the framer to be accessed. In multiplexed bus applications, the A[7:0] pins
should be connected to the D[7:0] pins, and A[11:0] must have a valid register address when the ALE pin
goes low. A11 is the MSB; A0 is the LSB.
ALE
I
CPU Bus Address Latch Enable. This pin controls the address latch for the A[11:0] inputs. When ALE is
high, the latch is transparent. On the falling edge of ALE, the latch samples and holds the A[11:0] inputs.
In nonmultiplexed bus applications, ALE should be wired high. In multiplexed bus applications, A[7:0]
should be connected to D[7:0], and the falling edge of ALE latches the address.
CS
I
CPU Bus Chip Select, Active Low. The host processor selects the device for read or write access by
driving this pin low.
WR (R/W)
I
CPU Bus Write Enable (CPU Bus Read/Write Select), Active Low. In Intel mode (MOT = 0),
WR controls
write accesses to the device. In Motorola mode (MOT = 1), R/
W specifies whether a read or a write
access is to occur.
RD (DS)
I
CPU Bus Read Enable (CPU Bus Data Strobe), Active Low. In Intel mode (MOT = 0),
RD controls read
accesses to the device. In Motorola mode (MOT = 1),
DS controls both read and write accesses to the
device, while the R/
W pin specifies the type of access.
INT
O
CPU Bus Interrupt, Open Drain, Active Low. This pin is driven low by the device if one or more unmasked
interrupt sources within the device are active.
INT remains low until the interrupt is serviced or masked.
SCLK
I
System Clock. An ungapped clock with frequency between 33MHz and 52MHz must be provided to this
pin to run certain logic in the CPU bus port. The use of this clock allows the transmit and receive clocks
(TICLK and RCLK) to be gapped, if desired, without affecting the CPU bus timing. This pin can be
connected to TICLK or RCLK if the signal on one of those pins is an ungapped clock.
5.6 JTAG Interface Pins
NAME
TYPE
FUNCTION
JTCLK
I
JTAG IEEE 1149.1 Test Serial Clock. This pin is used to shift data into JTDI on the rising edge and out of
JTDO on the falling edge. If not used, this pin should be wired high.
JTDI
I
JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10k
W Pullup). Test instructions and data are clocked in
on this pin on the rising edge of JTCLK. If not used, JTDI should be left unconnected or driven high.
JTDO
O
JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions are clocked out of this pin on the falling
edge of JTCLK. If not used, JTDO should be left open-circuited. This pin is in tri-state mode after
JTRST is
activated.
JTRST
I
JTAG IEEE 1149.1 Test Reset (Active-Low, Internal 10k
W Pullup). This pin is used to asynchronously
reset the test access port controller. At power-up,
JTRST must be driven low and then high. This action
sets the device into the boundary scan bypass mode, allowing normal device operation. If boundary scan
is not used, this pin should be held low.
JTMS
I
JTAG IEEE 1149.1 Test Mode Select (Internal 10k
W Pullup). This pin is sampled on the rising edge of
JTCLK and is used to place the test port into the various defined IEEE 1149.1 states. If not used, JTMS
should be left unconnected or driven high.
5.7 Supply, Test, and Reset Pins
NAME
TYPE
FUNCTION
RST
I
Global Hardware Reset (Active Low). When this pin is driven low, all of the framers in the device are reset
and all of the internal registers are forced to their default values. The device is held in the reset state as
long as this pin is low. The clocks (TICLK and RCLK) must be stable and in spec before this pin is driven
high. The device registers can be configured for operation after the reset is deactivated.
TEST
I
Factory Test Enable (Active-Low, Internal 10k
W Pullup). This pin should be left open-circuited.
HIZ
I
High-Z Control (Active-Low, Internal 10k
W Pullup). When this pin is low and JTRST is low, all outputs go to
the high-impedance mode. This pin can be left open-circuited by the user.
VSS
—
Digital Ground Reference. All VSS pins should be wired together.
VDD
—
Digital Positive Supply. 3.3V (
±5%). All VDD pins should be wired together.
相關(guān)PDF資料
PDF描述
DS3150TN IC LIU T3/E3/STS-1 IND 48-TQFP
DS3154N+ IC LIU DS3/E3/STS-1 QD 144CSBGA
DS3164+ IC ATM/PACKET PHY QUAD 400-BGA
DS3170+ IC TXRX DS3/E3 100-CSBGA
DS3172N+ IC TXRX DS3/E3 DUAL 400-BGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS31415 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock
DS31415_1107 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock
DS31415DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS31415 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS31415GN+ 制造商:Microsemi Corporation 功能描述:SINGLE DPLL TIMING IC W/APLL & 1588 CLOCK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:SINGLE DPLL TIMING IC W/APLL & 1588 CLOCK - Rail/Tube 制造商:Microsemi 功能描述:DPLL 256-Pin CSBGA
DS3141N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*