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參數(shù)資料
| 型號： | DS31412N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 37/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 12CH DS3/3 FRAMER 349-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 960mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
42 of 89
Register Name:
T3E3IR
Register Description:
DS3/E3 Information Register
Register Address:
1Bh
Bit #
7
6
5
4
3
2
1
0
Name
RUA1
T3AIC
E3Sn
N/A
EXZL
MBEL
FBEL
ZSCDL
Default
—
Note: The status bits in T3E3IR cannot cause a hardware interrupt to occur.
Bit 0: Zero-Suppression Codeword-Detected Latched (ZSCDL). This latched information bit is set to 1 when the
framer detects a B3ZS/HDB3 codeword. ZSCDL is cleared when the host processor writes a 1 to it and is not set
again until the framer has detected another B3ZS/HDB3 codeword. This bit has no meaning when the part is
configured to operate in binary mode (BIN = 1 in the MC1 register) and should be ignored. This status is still active
when the ZCSD control bit is set in the MC1 register.
Bit 1: F-Bit or FAS Error-Detected Latched (FBEL). This latched information bit is set to 1 when the framer
detects an error in either the F bits (DS3 mode) or the FAS word (E3 mode). FBEL is cleared when the host
processor writes a 1 to it and is not set again until the framer detects another error.
Bit 2: M-Bit Error-Detected Latched (MBEL). This latched information bit is set to 1 when the framer detects an
error in the M bits. MBEL is cleared when the host processor writes a 1 to it and is not set again until the framer
detects another error in the M bits. This status bit has no meaning in the E3 mode (DS3M = 0 in register MC1) and
should be ignored.
Bit 3: Excessive Zeros-Detected Latched (EXZL). This latched information bit is set to 1 when the framer detects
a consecutive string of either three or more 0s (DS3 mode) or four or more 0s (E3 mode). EXZL is cleared when
the host processor writes a 1 to it and is not set again until the framer detects another excessive zero event. This
status is not active when the framer is configured to operate in binary mode (BIN = 1 in register MC1).
Bit 5: E3 National Bit (E3Sn). This real-time status bit reports the incoming E3 National Bit (Sn). E3Sn is loaded at
the start of each E3 frame as the Sn bit is decoded.
Bit 6: DS3 Application ID Channel Status (T3AIC). This real-time status bit indicates whether the incoming DS3
data stream is in C-Bit Parity format or M23 format. In the DS3 frame, the first C bit in M-subframe 1 is the
application identification channel (AIC). ANSI T1.107 mandates that the AIC must be set to 1 for C-Bit Parity
applications and must be toggling between 0 and 1 for M23 application (since it is a stuff control bit). The T3AIC
information bit is set to 1 when the framer detects that the AIC is set to 1 for 1020 times or more out of 1024
consecutive M-frames (109ms). T3AIC is cleared when the framer detects that the AIC is set to 1 less than 1020
times out of 1024 consecutive M-frames (109ms). This status bit has no meaning in the E3 mode and should be
ignored.
Bit 7: Receive Unframed All Ones (RUA1). This real-time status bit indicates that the framer is receiving an
unframed all-ones signal. This status bit is valid in both DS3 and E3 modes and has the same function in both
modes. The set and clear criteria for RUA1 are listed in Table 7-E and Table 7-F.
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