參數(shù)資料
型號: CH7002D
廠商: Electronic Theatre Controls, Inc.
英文描述: Scalable VGA to NTSC/PAL Encoder
中文描述: 可擴(kuò)展顯卡至NTSC / PAL編碼器
文件頁數(shù): 4/36頁
文件大?。?/td> 199K
代理商: CH7002D
CHRONTEL
Table 1. Pin Description
(continued)
CH7002D
4 201-0000-029 Rev6.1, 8/2/99
44-Pin
PLCC
Type
Symbol
Description
22
Out
C
Chrominance Output
A 75
termination resistor, with short traces, should be attached between C
and ground for optimum performance. Use of additional filters is discussed in
the
Application Information
section.
Position Controls (low-to-high transition, internal pull-up)
UP, DOWN, LEFT, and RIGHT, allows the screen display position to be
moved incrementally, in each respective direction, for every toggle of this pin
to ground. An internal schmitt trigger minimizes switch bounce problems.
These pins may be connected directly to the power supply or ground.
Reset (active low) /Display Mode Select [0] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), the RESET*/DM0 pin becomes
RESET*. In this mode, when RESET* is held high (default), the chip is in
operating state, and when RESET* is pulled low, the entire chip is reset and
initialized to its power-up state.
When the PMODE pin is pulled low, this pin becomes DM0, which combined
with DM1 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described in
Application Information
and
Registers
and Programming
sections.
Serial Data/Display Mode Select [1] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SD, the serial
data pin of the I
2
C interface port.
When the PMODE pin is pulled low, this pin becomes DM1, which combined
with DM0 and DM2, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described under the programming section.
Serial Clock/Display Mode Select [2] (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes SC, the serial
clock pin of the I
2
C interface port.
When the PMODE pin is pulled low, this pin becomes DM2, which combined
with DM0 and DM1, provides for pin-programming of the 7002 display mode.
The pin-programming is “mux-ed” with the Display Mode register selections.
All applicable modes are described in the
Registers and Programming
and
Application Information
sections.
External Clock/Sample Delay (bit 3) (internal pull-up)
The function of this dual use pin is determined by the state of the PMODE pin.
When the PMODE pin is kept high (default), this pin becomes XCLK or
external clock, which accepts an external pixel clock input.
When the PMODE pin is pulled low, this pin becomes SD3 or Sample Delay,
the function corresponding to bit 3 of the Sample Delay register, which
provides the following selection:
SD3 Sample Delay Selected
1 20 ns nominal delay
0 0 delay (default)
This pin-programming is “mux-ed” with the Sample Delay register (bit 3). All
related modes are described in the
Registers and Programming
section.
Vertical Sync Input
This pin accepts the vertical sync output from the VGA card. The capacitive
loading on this pin should be kept to a minimum.
Horizontal Sync Input
This pin accepts the horizontal sync output from the VGA card. The
capacitive loading on this pin should be kept to a minimum. Refer to the
Application Information
section for PC Board layout considerations.
9, 11, 12,
13
In
UP,
DOWN,
LEFT,
RIGHT
28
In
RESET*/D
M0
29
In/Out
SD/DM1
30
In
SC/DM2
32
In
XCLK/SD3
35
In
V
34
In
H
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