參數(shù)資料
型號(hào)： CH7002D
廠商： Electronic Theatre Controls, Inc.
英文描述： Scalable VGA to NTSC/PAL Encoder
中文描述： 可擴(kuò)展顯卡至NTSC / PAL編碼器
文件頁(yè)數(shù)： 31/36頁(yè)
文件大?。?/td> 199K
代理商： CH7002D
CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
31
If a 2-layer design is used, the layer utilization should be:
Layer 1: Analog interconnects, area-filled power supply planes
Layer 2: Digital interconnects, area-filled ground plane
Placement Considerations
The CH7002 device should be placed in close proximity with other analog components it connects to, or shares
power connections. Conversely, the device should be located as far as possible from noise-producing digital
components such as microprocessors, DRAM arrays, system clock generators, etc.
Power Distribution and Decoupling
As previously described, the CH7002 has three separate sets of power connections to the external system. Normally,
all power supply connections will be derived from a single board level supply bus. If the system includes other
potentially noisy digital components, it is best to use a separate linear voltage regulator to power the CH7002.
The three power buses should be isolated from each other through the use of ferrite beads. Surface mount beads,
having a nominal impedance of 55-60 ohms at 100MHz, are usually effective.
It is critically important that all power supply connections be effectively decoupled. Each power pin should be
decoupled to its “associated” ground pin (see Table 7), with a high-quality ceramic surface mount capacitor. These
capacitors should be placed as close as possible to the device pins; the preferred value is 0.1 uF. In the case of
especially noisy environments, greater decoupling effectiveness can be achieved by adding a 0.01 uF ceramic cap in
parallel with each 0.1 uF cap. The 0.01 uF cap provides greater bypassing of very high frequency noise. Each
CH7002 ground pin should be directly connected to its respective decoupling capacitor lead; then, both the pin and
the lead should be connected to the ground plane. If possible, a physical connecting trace between the CH7002
ground pin and the capacitor lead should be present on the connecting layer, rather than relying on the ground plane
alone for the connections. All ground traces should be short and wide, with multiple ground vias to minimize
parasitic inductance. A recommended power supply isolation and decoupling strategy is detailed in
Figure 27
on
page 33.
Table 7. Power and Ground Pin Decoupling
Power Pin
Pin Number
Associated Ground Pin
DVDD1
8
10
DVDD2
14
16
DVDD3
33
31
VDD1
25
21
AVDD1
44
2
AVDD2
7
6
AVDD3
37
39
AVDD4
40
42
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CH7002D-V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Scalable VGA to NTSC/PAL Encoder
CH7003B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder
CH7003B-T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder
CH7003B-V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder
CH7004C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder with Macrovision
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