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參數(shù)資料
| 型號： | CH7002D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Scalable VGA to NTSC/PAL Encoder |
| 中文描述： | 可擴(kuò)展顯卡至NTSC / PAL編碼器 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大?。?/td> | 199K |
| 代理商： | CH7002D |
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CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
27
Application Information
Figure 24
on page 28 shows the basic power, input, control, and output connections of the CH7002 necessary to
generate TV output from VGA analog (RGB) input signals. This connection shows the most simplified
configuration, in which all control of the CH7002 modes and features are accomplished using the I
2
C
serial control
port.
Basically, the CH7002 receives analog RGB as well as TTL-compatible horizontal and vertical sync signals from
the VGA interface. In the configuration shown, the pixel clock is regenerated internally to the CH7002 using a
“genlock” PLL and the HSYNC input as a reference frequency. A 14.31818 oscillator provides a frequency
reference for color subcarrier generation.
Power Connections
The CH7002 has three separate sets of power connections to the external system. The AVDD connections supply
power to the video ADCs and genlock PLL. The DVDD connections power the digital circuits, including memory,
control, and signal processing functions. Finally, the VDD connection powers the S-Video and composite video
DAC’s and output circuits.
Normally, all power supply connections will be derived from a single board level supply bus. If the system includes
other potentially noisy digital components, it is best to use a separate linear voltage regulator to power the CH7002.
As with all video frequency analog devices, careful attention to power supply distribution is essential to achieve
optimum performance. A detailed discussion of recommended power supply distribution and decoupling methods is
provided in the section entitled
PC Board Layout Guidelines
.
Analog Input Connections
The CH7002 processes the video signals received on the RGB input pins. The first step in processing is to convert
the analog signals into corresponding digital values through the use of a triple, high-speed ADC. The analog input
pins accommodate signals ranging between 0 and 750 mV; this range is compatible with the standard output of a
VGA, properly terminated with a 37.5 ohms effective load.
The RC filter networks (see
Figure 24
on page 28) serve to bandlimit the input signals to avoid aliasing artifacts.
Typical Use Configuration
The VGA input configured for applications that do not require RGB buffering before the monitor is shown in
Figure 24
. In this configuration, 75
input termination must be guaranteed by: termination by the monitor
connection, discrete 75
resistors on the PCB, or a dummy 75
termination connector. The total RGB trace on the
PCB must be kept as short as possible to avoid cable reflection problems.
Refer to crystal manufacturer specifications for proper load capacitances. The optional variable tuning capacitor is
required only if the crystal oscillation frequency cannot be controlled to the required accuracy. The capacitance
value for the tuning capacitor should be obtained from the crystal manufacturer.
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| CH7002D-V | Scalable VGA to NTSC/PAL Encoder |
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相關(guān)代理商/技術(shù)參數(shù) |
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| CH7002D-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Scalable VGA to NTSC/PAL Encoder |
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| CH7004C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder with Macrovision |
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