參數(shù)資料
型號(hào)： CH7002D
廠商： Electronic Theatre Controls, Inc.
英文描述： Scalable VGA to NTSC/PAL Encoder
中文描述： 可擴(kuò)展顯卡至NTSC / PAL編碼器
文件頁(yè)數(shù)： 19/36頁(yè)
文件大?。?/td> 199K
代理商： CH7002D
CHRONTEL
CH7002D
201-0000-029 Rev 6.1, 8/2/99
19
Register Address Byte (RAB)
AutoInc
Register Address Auto-Increment - to facilitate sequential r/w of registers.
“1”:
Auto-Increment enabled (auto-increment mode).
Write: After writing data into a register, the Address Register will automatically be
incremented by one.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will automatically be incremented by one. The
Address Register will not be changed for the first read after an RAB.
“0”:
Auto-Increment disabled (alternating mode).
Write: After writing data into a register, the Address Register will remain unchanged until a
new RAB is written.
Read: Before loading data from a register to the on-chip temporary register (getting ready to
be serially read), the Address Register will remain unchanged.
AR[3:0]
Specifies the Address of the Register to be Accessed.
This register address is loaded into the Address Register of the CH7002. The R/W* access,
which follows, is directed to the register specified by the content stored in the Address Register.
The following two sections describe the operation of the serial interface for the four combinations of R/W* = 0,1
and AutoInc = 0,1.
CH7002 Write Cycle Protocols (R/W = 0)
Data transfer with acknowledge is required. The acknowledge-related clock pulse is generated by the master-
transmitter. The master-transmitter releases the SD line (HIGH) during the acknowledge clock pulse. The slave-
receiver must pull down the SD line, during the acknowledge clock pulse, so that it remains stable LOW during the
HIGH period of the clock pulse. The CH7002 always acknowledges for writes (see
Figure 19
). Note that the
resultant state on SD is the wired-AND of data outputs from the transmitter and receiver.
Figure 19: Acknowledge on the Bus
Figure 20
shows two consecutive alternating write cycles for AutoInc = 0 and R/W = 0. The byte of information,
following the Register Address Byte (RAB), is the data to be written into the register specified by AR[3:0]. If
AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on.
B7
B6
B5
B4
B3
B2
B1
B0
1
AutoInc
X
X
AR[3]
AR[2]
AR[1]
AR[0]
SC from
Master
Data Output
By the CH7002
Start
Condition
2
Data Output
By Master-Transmitter
1
8
9
not acknowledge
acknowledge
clock pulse for
acknowledgement
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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CH7003B-V 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Digital PC to TV Encoder
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