參數(shù)資料
型號(hào)： BU-62864
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 7/56頁(yè)
文件大小： 368K
代理商： BU-62864
7
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
MEMORY SPACE
This bit controls the device's response to memory space access-
es. A value of 0b disables the device response. A value of 1b
allows the device to respond to memory space accesses. The
value after RST# is 0b.
PCI STATUS REGISTER
This register records status information for PCI bus related
events. Reads to this register behave normally, but writes can
only reset bits. A bit is reset whenever the register is written and
the data in the corresponding bit location is a 1.
DETECTED PARITY ERROR
This bit will be set by the device whenever it detects a parity
error, even if the Parity Error Control bit in the PCI Control regis-
ter is 0b.
SIGNALED SYSTEM ERROR
This bit indicates when the device has asserted SERR#. The
value after RST# is 0b.
SIGNALED TARGET ABORT
This bit is set whenever the device terminates a transaction with
a Target-Abort.The value after RST# is 0b.
DEVSEL# TIMING
The PCI enhanced Mini-ACE is 01b, medium.
FAST BACK-TO-BACK CAPABLE
This bit is set to 1b and indicates that the device is capable of
accepting fast back-to-back transactions.
RESERVED
These bits are read-only and return zeroes when read.
SUBSYSTEM VENDOR ID/SUBSYSTEM DEVICE ID
This field is an alias of the Vendor ID/Device ID fields in
Configuration Register 00h.
BASE ADDRESS REGISTERS
Base Address Registers are used to implement ACE memory
space (BAR0) and ACE register space (BAR1). Base Address
Registers 2 through 5 are not used.
BAR0
BAR0 is used to access ACE memory space. The ACE is allot-
ted a maximum of 64K words, 128K bytes, for its memory space.
BAR0 will read back as FFFE0000 after all Fs are written to it.
BAR0 will read back the same for both the 4K word ACE parts
(BU-62743/843) and the 64K word ACE (BU-62864).
0400h
BC/RT/MT with 4K of RAM (BU-62843)
0402h
BC/RT/MT with 64K of RAM (BU-62864)
0404h
RT Only with 4K of RAM (BU-62743)
TABLE 4. DEVICE ID FIELD MAPPING
DEVICE ID
PART VALUE
15:10
Reserved, 0s
9
0
8
SERR# Enable
7
0
TABLE 5. PCI COMMAND REGISTER
BIT
DESCRIPTION
6
Parity Error Control
5:2
0
1
Memory Space
0 (LSB)
0
31
Detected Parity Error
30
Signaled System Error
29:28
0
27
Signaled Target Abort
TABLE 6. PCI STATUS REGISTER
BIT
DESCRIPTION
26:25
DEVSEL# Timing = 01 (medium)
24
0
23
Fast Back-to-Back Capable = 1
22:21
0
20:16
Reserved, 0s
00000 - 1FFFC
PCI ENHANCED Mini-ACE Memory Space
TABLE 7. (BAR0) ACE MEMORY
ADDRESS OFFSET
DEFINITION
PCI ENHANCED MINI-ACE MEMORY SPACE
The least significant bit (LSB) of the PCI address is dropped to
form the ACE memory address.
BAR1
BAR1 is used to access ACE register locations.The ACE is allot-
ted a maximum of 4K bytes for its register space. BAR1 will read
back as FFFFF000h after all Fs are written to it. All ACE register
locations are accessible through the PCI host via the BAR1 off-
sets 000h to 0FCh.The PCI-to-ACE interface control/status reg-
isters are at 800h to 81Ch. PCI accesses outside of these spe-
cific regions (e.g., to offset 100h or 820h, etc.) will produce
Target Aborts.
PCI ENHANCED MINI-ACE REGISTER SPACE
Register accesses are on a 32-bit boundary: the last 2 bits of the
PCI address are dropped to form the ACE address. (e.g. 000 =
ACE Reg 0, 004 = ACE Reg1, 008 = ACE Reg2, etc.).
PCI_INTERRUPT ACTIVE
When set to '1', indicates that PCI Enhanced Mini-ACE has
asserted it's interrupt pin.The three possible sources (if enabled
and active) are the Enhanced Mini-ACE, fail-safe timer and
BAR1 DRR_DATA_DISCARD.
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