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參數(shù)資料
| 型號： | BU-62864 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？ |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 368K |
| 代理商： | BU-62864 |
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20
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
NON-TEST REGISTER FUNCTION SUMMARY
A summary of the PCI Enhanced Mini-ACE's 24 non-test regis-
ters follows.
INTERRUPT MASK REGISTERS #1 AND #2
Interrupt Mask Registers #1 and #2 are used to enable and dis-
able interrupt requests for various events and conditions.
CONFIGURATION REGISTERS #1 AND #2
Configuration Registers #1 and #2 are used to select the PCI
Enhanced Mini-ACE's mode of operation, and for software con-
trol of RT Status Word bits, Active Memory Area, BC Stop-On-
Error, RT Memory Management mode selection, and control of
the Time Tag operation. Note that the LEVEL/PULSE INTER-
RUPT REQUEST bit in Configuration Register #2 MUST be set
to 1 for correct PCI operation.
START/RESET REGISTER
The Start/Reset Register is used for "command" type functions
such as software reset, BC/MT Start, Interrupt reset, Time Tag
Reset, Time Tag Register Test, Initiate RAM self-test, Clear self-
test register, and Clear RT Halt. The Start/Reset Register also
includes provisions for stopping the BC in its auto-repeat mode,
either at the end of the current message or at the end of the cur-
rent BC frame.
BC/RT COMMAND STACK REGISTER
The BC/RT Command Stack Register allows the host CPU to
determine the pointer location for the current or most recent
message.
BC INSTRUCTION LIST POINTER REGISTER
The BC Instruction List Pointer Register may be read to deter-
mine the current location of the Instruction List Pointer for the
Enhanced BC mode.
BC CONTROL WORD/RT SUBADDRESS CONTROL
WORD REGISTER
In BC mode, the BC Control Word/RT Subaddress Control Word
Register allows host access to the current word or most recent
BC Control Word.The BC Control Word contains bits that select
the active bus and message format, enable off-line self-test,
masking of Status Word bits, enable retries and interrupts, and
specify MIL-STD-1553A or -1553B error handling. In RT mode,
this register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
NOTE: Please see Appendix “F” of the Enhanced Mini-ACE
Users Guide for important information applicable only to RT
MODE operation, enabling of the interrupt status queue and
use of specific non-message interrupts.
used to select the memory management scheme and enable
interrupts for the current message.
TIME TAG REGISTER
The Time Tag Register maintains the value of a real-time clock.
The resolution of this register is programmable from among 2, 4,
8, 16, 32, and 64 μs/LSB.The Start-of-Message (SOM) and End-
of-Message (EOM) sequences in BC, RT, and Message Monitor
modes cause a write of the current value of the Time Tag
Register to the stack area of the RAM.
INTERRUPT STATUS REGISTERS #1 AND #2
Interrupt Status Registers #1 and #2 allow the host processor to
determine the cause of an interrupt request by means of one or
two read accesses. The interrupt events of the two Interrupt
Status Registers are mapped to correspond to the respective bit
positions in the two Interrupt Mask Registers. Interrupt Status
Register #2 contains an INTERRUPT CHAIN bit, used to indicate
an interrupt event from Interrupt Status Register #1.
CONFIGURATION REGISTERS #3, #4, AND #5
Configuration Registers #3, #4, and #5 are used to enable many
of the PCI Enhanced Mini-ACE's advanced features that were
implemented by the prior generation products, the ACE and Mini-
ACE (Plus). For BC, RT, and MT modes, use of the ENHANCED
MODE enables the various read-only bits in Configuration
Register #1. For BC mode, ENHANCED mode features include
the expanded BC Control Word and BC Block Status Word, addi-
tional Stop-On-Error and Stop-On-Status Set functions, frame
auto-repeat, programmable intermessage gap times, automatic
retries, expanded Status Word Masking, and the capability to
generate interrupts following the completion of any selected
message.For RT mode, the enhanced mode features include the
expanded RT Block Status Word, combined RT/Selective
Message Monitor mode, internal wrapping of the RTFAIL output
signal to the RTFLAG RT Status Word bit, and the alternate (fully
software programmable) RT Status Word. For MT mode, use of
the enhanced mode enables the Selective Message Monitor, the
combined RT/Selective Monitor modes, and the monitor trigger-
ing capability.
RT/MONITOR DATA STACK ADDRESS REGISTER
The RT/Monitor Data Stack Address Register provides a
read/writable indication of the last data word stored for RT or
Monitor modes.
BC FRAME TIME REMAINING REGISTER
The BC Frame Time Remaining Register provides a read-only
indication of the time remaining in the current BC frame. In the
enhanced BC mode, this timer may be used for minor or major
frame control, or as a watchdog timer for the BC message
sequence control processor.The resolution of this register is 100
μs/LSB.
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