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參數(shù)資料
| 型號(hào)： | BU-62864 |
| 英文描述： | MIL-STD-1553 Components |PCI-Enhanced Mini-ACE? |
| 中文描述： | 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？ |
| 文件頁數(shù)： | 28/56頁 |
| 文件大?。?/td> | 368K |
| 代理商： | BU-62864 |
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Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
GENERAL PURPOSE QUEUE
The PCI Enhanced Mini-ACE BC allows for the creation of a gen-
eral purpose queue.This data structure provides a means for the
message sequence processor to convey information to the BC
host. The BC op code repertoire provides mechanisms to push
various items on this queue. These include the contents of the
Time Tag Register, the Block Status Word for the most recent
message, an immediate data value, or the contents of a speci-
fied memory address.
FIGURE 5 illustrates the operation of the BC General Purpose
Queue. Note that the BC General Purpose Queue Pointer
Register will always point to the next address location (modulo
64); that is, the location following the last location written by the
BC message sequence control engine.
If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER
interrupt will be issued when the value of the queue pointer
address rolls over at a 64-word boundary.
REMOTE TERMINAL (RT) ARCHITECTURE
The PCI Enhanced Mini-ACE's RT architecture builds upon that
of the ACE and Mini-ACE.The PCI Enhanced Mini-ACE provides
multiprotocol support, with full compliance to all of the common-
ly used data bus standards, including MIL-STD-1553A, MIL-
STD-1553B, Notice 2, STANAG 3838, General Dynamics
16PP303, and McAirA3818, A5232, and A5690. For the PCI
Enhanced Mini-ACE RT mode, there is programmable flexibility
enabling the RT to be configured to fulfill any set of system
requirements. This includes the capability to meet the MIL-STD-
1553A response time requirement of 2 to 5 μs, and multiple
options for mode code subaddresses, mode codes, RT status
word, and RT BIT word.
The PCI Enhanced Mini-ACE RT protocol design implements all
of the MIL-STD-1553B message formats and dual redundant
mode codes. The design has passed validation testing for MIL-
STD-1553B compliance. The PCI Enhanced Mini-ACE RT per-
forms comprehensive error checking, word and format validation,
and checks for various RT-to-RT transfer errors. One of the main
features of the PCI Enhanced Mini-ACE RT is its choice of mem-
ory management options.These include single buffering by sub-
address, circular buffering by individual subaddresses, and glob-
al circular buffering for multiple (or all) subaddresses.
Other features of the PCI Enhanced Mini-ACE RT include a set
of interrupt conditions, an interrupt status queue with filtering
based on valid and/or invalid messages, internal command ille-
galization, programmable busy by subaddress, and multiple
options on time tagging.
RT MEMORY ORGANIZATION
TABLE 54 illustrates a typical memory map for a PCI Enhanced
Mini-ACE RT with 4K RAM. The two Stack Pointers reside in
fixed locations in the shared RAM address space: address
0100h (PCI BAR0 + 200h) for the Area A Stack Pointer and
address 0104h (PCI BAR0 + 208h) for the Area B Stack Pointer.
In addition to the Stack Pointer, there are several other areas of
LAST LOCATION
BC GENERAL
PURPOSE QUEUE
(64 Locations)
BC GENERAL
PURPOSE QUEUE
POINTER
REGISTER
NEXT LOCATION
FIGURE 5. BC GENERAL PURPOSE QUEUE
Data Block 100
0FE0-0FFF
Data Block 6
0420-043F
Data Block 5
0400-041F
Command Illegalizing Table
0300-03FF
RESERVED
Data Block 1-4
0280-02FF
Data Block 0
0260-027F
(not used)
0248-025F
Busy Bit Lookup Table
0240-0247
Lookup Table B
01C0-023F
Lookup Table A
0140-01BF
Mode Code Data
0110-013F
Mode Code Selective Interrupt Table
0108-010F
Global Circular Buffer B Pointer
Stack Pointer B
0105
0104
RESERVED
0102-0103
Global Circular Buffer A Pointer
Stack Pointer A
0101
0100
Stack A
0000-00FF
DESCRIPTION
WORD
ADDRESS
(HEX)
0106-0107
1FC0-1FFE
0840-087E
0800-083E
0600-07FE
0500-05FE
04C0-04FE
0490-04BE
0480-048E
0380-047E
0280-037E
0220-027E
0210-021E
020A
0208
0204-0206
0202
0200
0000-01FE
PCI BAR0
OFFSET
(HEX)
020C-020E
TABLE 54. TYPICAL RT MEMORY MAP
(SHOWN FOR 4K RAM)
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