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參數(shù)資料
| 型號： | BU-69200 |
| 英文描述： | MIL-STD-1553 Components |ACE-Core |
| 中文描述： | 符合MIL - STD - 1553器件|進洞核心 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 373K |
| 代理商： | BU-69200 |
ACECore MIL-STD-1553
Intellectual Property (IP) Core
MODEL: BU-69200
DESCRIPTION
The ACECore Intellectual Property (IP) is based on the architecture of DDC's powerful Enhanced Mini-ACE
MIL-STD-1553 protocol engine. As such, it provides compatibility with all previous and current generations of DDC
components, including AIM-HY, AIM-HY'er, ACE, Mini-ACE, as well as Enhanced Mini-ACE, PCI Enhanced Mini-ACE,
and μ-ACE.
As a result, the ACECore IP brings a legacy of demonstrated performance in a myriad of air, land, and space
applications. Further, this compatibility enables designers to leverage investments in legacy ACE software and to
accelerate development efforts using DDC's components early in their design phase.
The ACECore provides VHDL core source code, VHDL test bench, and supporting documentation, thus enabling
designers to instantiate the architecture in a variety of PLD, FPGA, or ASIC System on a Chip (SoC) implementations.
The ACECore can be configured as BC/RT/MT, RT-only, or customized for your requirements. The core provides a
high degree of flexibility in terms of processor interface, memory architecture, and self-test functionality. To mini-
mize design risk, the design of the ACECore's manchester encoder/decoder is highly optimized for use with DDC's
5V or 3.3V transceivers.
The ACECore's advanced bus controller architecture provides methods to control message scheduling, along
with the means to minimize host overhead for asynchronous message insertion, facilitate bulk data transfers and
double buffering, and support various message retry and bus switching strategies.
The ACECore's remote terminal architecture provides flexibility in meeting all common MIL-STD-1553 protocols.
The choice of RT data buffering and interrupt options provides robust support for synchronous and asynchronous
messaging, while ensuring data sample consistency and supporting bulk data transfers. The ACECore message
monitor (and combined RT/Monitor) enables true message monitoring, with filtering on an RT address/T-R bit/sub-
address basis. The ACECore includes provides robust built-in self-tests for protocol, transceivers, and RAM.
All trademarks are the property of their respective owners
2002 Data Device Corporation
FEATURES
Modular and Universally
Synthesizable Code for Enhanced
Mini-ACE
-
Industry Standard, Proven
Design
-
Use Enhanced Mini-ACE
Hybrid
for Prototyping
Includes VHDL Design and VHDL
Test Bench Code
BC/RT/Monitor and RT-Only
Configurations.
Single Clock Domain, Selectable
for 10, 12, 16, or 20 MHz
Operation
Fully Synchronous Design
Approximately 20,000 ASIC Gates
for BC/RT/MT Instantiation, Highly
Optimized Design
Provision for up to 64K Words Off-
Core Buffer RAM, with Optional
RAM Parity Bit
Provision for Off-Core Built-In
Self-Test ROM
On-Core Buses are Unidirectional
(not tri-state). Tri-State Buses May
be Created Using Off-Core
Buffers
Instantiate on FPGAs or ASICs
Passed MIL-STD-1553 RT Validation
Testing
Compatible with DDC
Transceivers
Complete Documentation
Provided
Scalable to Higher Bit Rates
Applications:
-
Space/Rad Hard Applications
-
High Volume Applications
www.ddc-web.com
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