參數(shù)資料
型號： BU-69200
英文描述： MIL-STD-1553 Components |ACE-Core
中文描述： 符合MIL - STD - 1553器件|進(jìn)洞核心
文件頁數(shù)： 3/4頁
文件大?。?/td> 373K
代理商： BU-69200
Data Device Corporation
www.ddc-web.com
BU-69200
REV CODE 1
DDC
on
Board
Autonomous Built-In Self-Test Capability
- Protocol Self-Test
- RAM Self-Test
- Online Loopback Test
- Capability to Support Channel A-to-Channel B
Wraparound Test
- Capability to Test Transmitter Timeout Function
- Protocol Self-Test May be Run From External Host
Host and Memory Interface Configurations
- Shared RAM, Up to 64K X 16 or 64K X 17
(with RAM parity)
- 16-bit Address, 16-bit or 8-bit Data Path
- "Zero Wait State" Interface
(no hardware acknowledge) for Microcontrollers
- Support of DMA Configuration,
Enabling Core Access of RAM on Host Processor Bus
- Supports Use of External Dual Port RAM
Development Environment/Tools
- DDC Development Tools: Mentor Graphics
Workstation; Renoir Design Entry (Including for Block
Diagrams); Leonardo Synthesizer; Model Technology
Simulation Tool
- Sample Synthesis Scripts
- VHDL Test Bench
Miscellaneous
- Reset Philosophy: Hardware and Software Mechanisms
for Resetting All Flip-Flops
- No On-Chip Tri-State Buses.
DDC 3.3V
or 5V Dual
Transceiver
Decoder
Encoder
Decoder
Encoder
Protocol State
Machines:
BC
RT
Monitor
Registers:
Configuration
Interrupts
Self-Test
Other Functions
Interrupt
Logic
Host Interface
Buffers and
Logic
Shared RAM
Interface
Built-in
Self-Test Logic
Self-Test
ROM
(4K X 24
optional)
Shared RAM
(up to 64K X 17)
DATA
ADDRESS
CONTROL
INT*
ACECore Functional Blocks
Figure 1
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