參數(shù)資料
型號(hào)： BU-62864
英文描述： MIL-STD-1553 Components |PCI-Enhanced Mini-ACE?
中文描述： 符合MIL - STD - 1553器件|的PCI增強(qiáng)迷你ACE論壇？
文件頁(yè)數(shù)： 51/56頁(yè)
文件大?。?/td> 368K
代理商： BU-62864
51
Data Device Corporation
www.ddc-web.com
BU-62743/62843/62864
A-03/03-1M
FRAME# (I)
44
Frame.This signal is driven by the current bus master and identifies both the beginning
and duration of a bus operation.When FRAME# is first asserted, it indicates that a bus
transaction is beginning and that valid addresses and a corresponding bus command
are present on the AD[31:0] and C/BE[3:0] lines, qualified by PCI_CLK.When FRAME#
is deasserted the transaction is in the final data phase or has been completed.
IRDY# (I)
45
TRDY# (O)
46
STOP# (O)
48
IDSEL (I)
33
Device Select.This signal is sourced by an active target upon decoding that its address and
bus commands are valid.For bus masters, it indicates whether any device has decoded the
current bus cycle.
DEVSEL# (O)
47
Initialization Device Select.This pin is used as a chip select during configuration read
or write operations.
TABLE 72. PCI BUS CONTROL SIGNALS
(Note that all signals listed, except INTA#, are sampled on the rising edge of PCI_CLK)
SIGNAL NAME
DESCRIPTION
PIN (F & G PACKAGE)
Parity Error.This pin is used for reporting parity errors during the data portion of the bus
transaction for all cycles except a Special Cycle.It is sourced by the agent receiving data and
driven active two clocks following the detection of an error.This signal is driven inactive (high)
two clocks prior to returning to the tristate condition.
PERR# (O)
49
System Error.This pin is used for reporting address parity errors, data parity errors on
Special Cycle commands, or any other condition having a catastrophic system impact.
SERR# (O)
50
Interrupt A.This pin is a level sensitive, active low interrupt to the host.
INTA# (O)
21
Initiator Ready.This signal is sourced by the bus master and indicates that the bus
master is able to complete the current data phase of a bus transaction. For write opera-
tions, it indicates that valid data is on the AD[31:0] pins. Wait states occur until both
TRDY# and IRDY# are asserted together.
Target Ready.This signal is sourced by the selected target and indicates that the target
is able to complete the current data phase of a bus transaction. For read operations, it
indicates that the target is providing valid data on the AD[31:0] pins. Wait states occur
until both TRDY# and IRDY# are asserted together.
Stop.The Stop signal is sourced by the selected target and conveys a request to the
bus master to stop the current transaction.
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