
ASIX ELECTRONICS CORPORATION
76
AX88796BLF / AX88796BLI
Appendix A3: 186-like (16-bit)
An example, AX88796B’s bus setting as 186 mode. (One external pull-up resister connect to EECK)
Read
Host Addr
A[5:0]
CSR Offset
0
Offset 1
Offset 0
0
1
Offset 1
Offset 0
1
2
Offset 3
Offset 2
2
3
Offset 3
Offset 2
3
4
Offset 5
Offset 4
4
5
Offset 5
Offset 4
5
6
Offset 7
Offset 6
6
7
Offset 7
Offset 6
7
8
Offset 9
Offset 8
8
9
Offset 9
Offset 8
9
A
Offset B
Offset A
A
B
Offset B
Offset A
B
C
Offset D
Offset C
C
D
Offset D
Offset C
D
E
Offset F
Offset E
E
F
Offset F
Offset E
F
10
(DP)
(DP)
(DP)
11
X
X
X
12
Offset 13
Offset 12
12
13
Offset 13
Offset 12
13
14
Offset 15
Offset 14
14
15
Offset 15
Offset 14
15
16
Offset 17
Offset 16
16
17
Offset 17
Offset 16
17
18
Offset 19
Offset 18
18
19
Offset 19
Offset 18
19
1A
Offset 1B
Offset 1A
1A
1B
Offset 1B
Offset 1A
1B
1C
Offset 1D
Offset 1C
1C
1D
Offset 1D
Offset 1C
1D
1E
No effect
Offset 1E
1E
1F
(Reset)
*1
(Reset)
*1
1F
*1 Read offset 1Fh register will reset AX88796B
Write
SD[15:8]
SD[7:0]
AX88796B
Host Addr
A[5:0]
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
SD[15:8]
SD[7:0]
AX88796B
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
(DP)
X
no effect
To Offset 1
no effect
To Offset 3
no effect
To Offset 5
no effect
To Offset 7
no effect
To Offset 9
no effect
To Offset B
no effect
To Offset D
no effect
To Offset F
(DP)
X
no effect
To Offset 13
no effect
To Offset 15
no effect
To Offset 17
no effect
To Offset 19
no effect
To Offset 1B no effect
no effect
To Offset 1D no effect
no effect
To Offset 1F no effect
To Offset 0
no effect
To Offset 2
no effect
To Offset 4
no effect
To Offset 6
no effect
To Offset 8
no effect
To Offset A
no effect
To Offset C
no effect
To Offset E
no effect
(DP)
X
To Offset 12 12
no effect
To Offset 14 14
no effect
To Offset 16 16
no effect
To Offset 18 18
no effect
To Offset 1A 1A
13
15
17
19
1B
To Offset 1C 1C
1D
To Offset 1E 1E
1F
SA0
SA1
SA2
SA3
SA4
SA5/FIFO_SEL
AEN/PSEN
SD[15:0]
RDn
WRn
IRQ
A0
A1
A2
A3
A4
A5
DATA[15:0]
RDn
WRn
INT
16-bit processor
AX88796B