參數(shù)資料
型號(hào)： AX88796BLI
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
中文描述： 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù)： 18/82頁
文件大?。?/td> 519K
代理商： AX88796BLI
ASIX ELECTRONICS CORPORATION
18
AX88796BLF / AX88796BLI
4.2.2 Packet Transmission
The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer during
transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0, 1).
When the AX88796B receives a command to transmit the packet pointed to by these registers, buffer memory data
will be moved into the FIFO as required during transmission. The AX88796B Controller will generate and append
the preamble, synch and CRC fields. AX88796B supports options of transmit queue function to enhance transmit
performance.
Original NE2000 Of Transmit Buffer
Options Of Transmit Buffer As A Ring
When active Transmit Buffer
Ring Enable (CR page3 of
offset
0Dh).
AX88796B
remote DMA write operation
will role over from last
transmit page to first transmit
page. Host no need reassign
RSAR0, RSAR1 again to fill
transmit data for first page.
Options Back-To-Back Transmission (TX Command Queue)
TPSR
TBCR
1, 0
TX Page Start Address (0x40)
Transmit buffer
Receive buffer
AX88796B
write default operation is
continue to write next address
even over transmit buffer
area. Host can do whole
memory read / write testing.
And host must handle the
transmit data do not overwrite
receive buffer area when
performing fill transmit data
to transmit buffer.
remote DMA
TX Page Start Address (0x40)
Transmit buffer
Receive buffer
Rx Page Start Register,
PSTART (CR page0, offset
01h)
Rx Page Start Register,
PSTART (CR page0, offset
01h)
TX Command Queue
Push In
Pop Out
When active TX Queue Enable
(offset 1Bh), Host can continue
Writing TXP (bit 2 of CR
register) to push TPSR and
TBCR1, 0 into AX88796B TX
command queue as long as
Transmit buffer has enough
vacancy and CTEPR (offset
1Ch) bit7 is ‘0’(Not full). After
current
packet
completely, MAC TX will pop
out next TPSR and TBCR1, 0
from TX Command Queue
then transmit this packet
following CSMA/CD protocol.
It is recommended to enable
this function to enhance TX
performance.
transmitted
AX88796B will report Current of Transmit End Page
CTEPR (offset 1Ch) when every packet transmits
completed.
Host can understand AX88796B current of transmitting
buffer point by reading CTEPR.
MAC TX
function block
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX88796C 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
AX88796L 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller
AX88796LF 制造商:ASIX 功能描述:10/100 MAC
AX88850 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX Repeater Controller
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