- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375384 > AX88796BLI (ASIX Electronics Corporation) Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | AX88796BLI |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| 中文描述： | 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 40/82頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AX88796BLI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
ASIX ELECTRONICS CORPORATION
40
AX88796BLF / AX88796BLI
5.1.20 Transmit Configuration Register (TCR)
Page0 Offset 0DH (Write)
Field
Name
Description
7
FDU
Full Duplex
This bit configure MAC media mode is Full Duplex or not.
0: Half duplex (Default)
1: Full duplex
This duplex setting was wire or with MCR bit-7. Each one goes high then configures MAC
as full-duplex. AX88796B will ignore this bit and MCR bit-7 when using internal PHY.
6
PD
Pad Disable
0: Pad will be added when packet length less than 60. (Default)
1: Pad will not be added when packet length less than 60.
5
RLO
Retry of late collision
0: Don’t retransmit packet when late collision happens. (Default)
1: Retransmit packet when late collision happens.
4:3
-
Reserved
2:1
LB1, LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode0 0 0 Normal operation (Default)
Mode 1 0 1 Internal AX88796B loop-back
Mode 2 1 0 PHY loop-back
No Define 1 1 Reserved
0
CRC
Inhibit CRC
0: CRC appended by transmitter. (Default)
1: CRC inhibited by transmitter.
5.1.21 Frame Alignment Error Tally Register (CNTR0)
Page0 Offset 0DH (Read)
Field
Name
Description
(Default = 00h)
7:0
CNTR0
This counter is incremented every time a packet is received with a Frame Alignment Error.
The packet must have been recognized by the address recognition logic. The counter is
cleared after the processor reads it.
5.1.22 Data Configuration Register (DCR)
Page0 Offset 0EH (Write)
Field
Name
Description
7:2
-
Reserved
1
-
Reserved
0
WTS
Word Transfer Select (Data Port Only)
0: Selects Data Port with byte-wide transfers. (Default)
1: Selects Data Port with word-wide transfers.
5.1.23 CRC Error Tally Register (CNTR1)
Page0 Offset 0EH (Read)
Field
Name
Description
(Default = 00h)
7:0
CNTR1
This counter is incremented every time a packet is received with a CRC error. The packet
must first be recognized by the address recognition logic. The counter is cleared after the
processor reads it.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
| AX9902MS | 2N and 2P-Channel Enhancement Mode Power MOSFET |
| AX9902MSA | 2N and 2P-Channel Enhancement Mode Power MOSFET |
| AXC-051 | ACTIVE FILTER FOR RIPPLE ATTENUATION 5A |
| AXC-051-R | ACTIVE FILTER FOR RIPPLE ATTENUATION 5A |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88796C | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller |
| AX88796CLF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88796L | 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796LF | 制造商:ASIX 功能描述:10/100 MAC |
| AX88850 | 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX Repeater Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。