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ASIX ELECTRONICS CORPORATION
3
AX88796BLF / AX88796BLI
FIGURES
F
IG
- 1 AX88796B B
LOCK
D
IAGRAM
.................................................................................................................................4
F
IG
- 2 AX88796B P
IN
O
UT
D
IAGRAM
...............................................................................................................................5
F
IG
- 3 I
NTERNAL
SRAM
MAP
..........................................................................................................................................11
F
IG
- 4 R
ECEIVE
B
UFFER
R
ING
..........................................................................................................................................15
F
IG
- 5 R
ECEIVE
B
UFFER
R
ING
A
T
I
NITIALIZATION
...........................................................................................................16
F
IG
- 6 TX / RX F
LOW CONTROL
......................................................................................................................................26
F
IG
- 7 EEPROM
CONNECTIONS
.......................................................................................................................................28
F
IG
- 8 PME
AND
IRQ
SIGNAL GENERATION
.....................................................................................................................29
F
IG
- 9 SMI
CONNECTIONS
................................................................................................................................................61
TABLES
T
AB
- 1 L
OCAL
CPU
BUS INTERFACE SIGNALS GROUP
........................................................................................................7
T
AB
- 2 10/100M
BPS
T
WISTED
-P
AIR
I
NTERFACES PINS GROUP
...........................................................................................7
T
AB
- 3 B
UILT
-
IN
PHY LED
INDICATOR PINS GROUP
.........................................................................................................7
T
AB
- 4 EEPROM
BUS INTERFACE SIGNALS GROUP
............................................................................................................7
T
AB
- 5
MISCELLANEOUS PINS GROUP
.................................................................................................................................8
T
AB
- 6 EEPROM
DATA FORMAT EXAMPLE
.......................................................................................................................9
T
AB
- 7 CSR A
DDRESS
M
APPING
.....................................................................................................................................10
T
AB
-
8 L
OCAL
M
EMORY
M
APPING
..................................................................................................................................10
T
AB
- 9 I
NTERNAL
SRAM M
AP
00H ~ 1FH.....................................................................................................................10
T
AB
- 10
INTERNAL
SRAM M
AP
0400H ~ 040FH ...........................................................................................................10
T
AB
- 11 B
YTE
L
ANE
M
APPING
........................................................................................................................................27
T
AB
- 12 P
OWER
M
ANAGEMENT
S
TATUSES
......................................................................................................................28
T
AB
- 13 P
AGE
0
OF
MAC C
ORE
R
EGISTERS
M
APPING
....................................................................................................31
T
AB
- 14 P
AGE
1
OF
MAC C
ORE
R
EGISTERS
M
APPING
....................................................................................................32
T
AB
- 15 P
AGE
2
OF
MAC C
ORE
R
EGISTERS
M
APPING
....................................................................................................33
T
AB
- 16 P
AGE
3
OF
MAC C
ORE
R
EGISTERS
M
APPING
....................................................................................................34
T
AB
- 17 T
HE
E
MBEDDED
PHY R
EGISTERS
......................................................................................................................53
T
AB
- 18 SMI M
ANAGEMENT
F
RAME
F
ORMAT
.................................................................................................................61
T
AB
- 19 MII M
ANAGEMENT
F
RAMES
-
FIELD
D
ESCRIPTION
.............................................................................................61