參數(shù)資料
型號： AT89C51SND2C-7FTUL
廠商： Atmel
文件頁數(shù)： 31/160頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝： 260
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB
外圍設(shè)備： 音頻，I²S，MP3，PCM，POR，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 64KB（64K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TFBGA
包裝： 托盤
其它名稱： AT89C51SND2C7FTUL
16
4341H–MP3–10/07
AT8xC51SND2C/MP3B
5.4
Registers
Table 5-1.
CKCON Register
CKCON (S:8Fh) – Clock Control Register
Reset Value = 0000 000Xb (AT89C51SND2C) or 0000 0000b (AT83SND2C)
Table 5-2.
PLLCON Register
PLLCON (S:E9h) – PLL Control Register
7
6
5
4
3
2
1
0
TWIX2
WDX2
-
SIX2
-
T1X2
T0X2
X2
Bit Number
Bit
Mnemonic
Description
7
TWIX2
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent).
Clear to select the peripheral clock as TWI clock input (X2 dependent).
6
WDX2
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
5
-
Reserved
The values read from this bit is indeterminate. Do not set this bit.
4
SIX2
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2 independent).
Clear to select the peripheral clock as UART clock input (X2 dependent)..
3
-
Reserved
The values read from this bit is indeterminate. Do not set this bit.
2
T1X2
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2 independent).
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
1
T0X2
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2 independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
0
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, F
CPU = FPER = FOSC/2).
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
7
6
5
4
3
2
1
0
R1
R0
-
PLLRES
-
PLLEN
PLOCK
Bit Number
Bit
Mnemonic
Description
7 - 6
R1:0
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
5 - 4
-
Reserved
The values read from these bits are always 0. Do not set these bits.
3
PLLRES
PLL Reset Bit
Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
2
-
Reserved
The value read from this bit is always 0. Do not set this bit.
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