A/D Converter Signal Description (AT8XSND2CMP3B
參數(shù)資料
型號(hào)： AT89C51SND2C-7FTUL
廠商： Atmel
文件頁數(shù)： 160/160頁
文件大小： 0K
描述： IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝： 260
系列： 89C
核心處理器： 8051
芯體尺寸： 8-位
速度： 40MHz
連通性： I²C，IDE/ATAPI，MMC，SPI，UART/USART，USB
外圍設(shè)備： 音頻，I²S，MP3，PCM，POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TFBGA
包裝： 托盤
其它名稱： AT89C51SND2C7FTUL
9
4341H–MP3–10/07
AT8xC51SND2C/MP3B
Table 4-11.
A/D Converter Signal Description (AT8XSND2CMP3B only)
Table 4-12.
External Access Signal Description
Note:
1. For ROM/Flash/ROMless Dice product versions only.
Table 4-13.
System Signal Description
Signal
Name
Type
Description
Alternate
Function
AIN1:0
I
A/D Analog Inputs
-
ADCREFP
I
Analog Positive Voltage Reference Input
-
ADCREFN
I
Analog Negative Voltage Reference Input
-
Signal
Name
Type
Description
Alternate
Function
A15:8
I/O
Address Lines
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
AD7:0
I/O
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the IDE
interface.
P0.7:0
ALE
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
-
ISP
I/O
ISP Enable Input (AT89C51SND2C Only)
This signal must be held to GND through a pull-down resistor at the falling
reset to force execution of the internal bootloader.
-
RD
O
Read Signal
Read signal asserted during external data memory read operation.
P3.7
WR
O
Write Signal
Write signal asserted during external data memory write operation.
P3.6
EA(1)
I
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations 0000H to FFFFH (RD).
-
Signal
Name
Type
Description
Alternate
Function
RST
I
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than V
IL is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset
by connecting a capacitor between this pin and V
DD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
-
TST
I
Test Input
Test mode entry signal. This pin must be set to V
DD.
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AT89C51-W 功能描述:8位微控制器 -MCU Microcontroller RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
AT89C52 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
AT89C52_00 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52_99 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Microcontroller with 8K Bytes Flash
AT89C52-12AA 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Bit Microcontroller with 8K Bytes Flash
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