參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 122/160頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標(biāo)準(zhǔn)包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS785UM1
7-59
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
S:
Shift - Read/Write
The Shift Mode is specified by selecting a value from
Table 7-15 and writing it to this field.
P:
Pixel - Read/Write
The number of bits per pixel that are output on the P[x]
pins is specified by selecting a value from Table 7-16 and
writing it to this field.
The Graphics Engine has a separate setting for this value,
which may or may not be the same.
0101
Blink to offset color single value mode
0110
Blink to offset color 888 mode (555,565)
0111
Undefined
1100
Blink dimmer single value mode
1101
Blink brighter single value mode
1110
Blink dimmer 888 mode (555,565)
1111
Blink brighter 888 mode (555,565)
Table 7-15. Output Shift Mode Table
S2
S1
S0
Shift Mode
0
1 - pixel per pixel clock (up to 24 bits wide)
0
1
1 - pixel mapped to 18 bits each pixel clock
0
1
0
2 - pixels per shift clock (up to 9 bits wide each)
0
1
4 - pixels per shift clock (up to 4 bits wide each)
1
0
8 - pixels per shift clock (up to 2 bits wide each)
1
0
1
2 2/3 3-bit pixels per clock over 8 bit bus
1
0
Dual Scan 2 2/3 3-bit pixels per clock over 8-bit bus
1
Undefined - Defaults to 1 - pixel per pixel clock
Table 7-16. Bits per Pixel Scanned Out
P2
P1
P0
Pixel Mode
0
pixel multiplexer disabled
0
1
4 bits per pixel
0
1
0
8 bits per pixel
0
1
do not use
Table 7-14. Blink Mode Definition Table (Continued)
M3
M2
M1
M0
Blink Mode
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