Copyright Cirrus Logic, Inc. 2011 (All Rights Reserved) 25 EP7312 High-Performance, Low-Power S" />
參數(shù)資料
型號: AT89C51SND2C-7FTUL
廠商: Atmel
文件頁數(shù): 124/160頁
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
標準包裝: 260
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外圍設(shè)備: 音頻,I²S,MP3,PCM,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TFBGA
包裝: 托盤
其它名稱: AT89C51SND2C7FTUL
DS508F2
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
25
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
EXPCLK
nCS
A
nMOE
HALF
WORD
D
nMWE
EXPRDY
WRITE
t
CSd
t
Ad
t
MWd
t
MWh
t
MWd
t
MWd
t
MWd
t
MWh
t
MWh
t
MWh
t
Ah
t
Ah
t
Ah
t
EXs
t
EXh
t
CSh
t
Dv
t
Dv
t
Dv
t
Dnv
t
Dnv
t
Dnv
t
Dv
t
HWd
t
WDd
Figure 10. Static Memory Burst Write Cycle Timing Measurement
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