參數(shù)資料
型號(hào)： AM49BDS640AH
廠商： Spansion Inc.
英文描述： Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
中文描述： 堆疊多芯片封裝（MCP），閃存和1.8伏，只有同時(shí)讀/寫(xiě)移動(dòng)存儲(chǔ)芯片的CMOS
文件頁(yè)數(shù)： 50/84頁(yè)
文件大?。?/td> 763K
代理商： AM49BDS640AH
48
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Synchronous/Burst Read
Note:
1. Addresses are latched on the first of either the active edge of CLK or the rising edge of AVD#.
Parameter
Description
66 MHz
54 MHz
Unit
JEDEC
Standard
t
IACC
Latency (Even address in Reduced wait-state
Handshake mode)
Max
56
69
ns
t
IACC
Latency (Standard Handshake or Odd
address in Reduced wait-state Handshake
mode
Max
71
87.5
ns
t
BACC
Burst Access Time Valid Clock to Output
Delay
Max
11
13.5
ns
t
ACS
Address Setup Time to CLK (Note 1)
Min
4
5
ns
t
ACH
Address Hold Time from CLK (Note 1)
Min
6
7
ns
t
BDH
Data Hold Time from Next Clock Cycle
Min
3
4
ns
t
CR
Chip Enable to RDY Valid
Max
11
13.5
ns
t
OE
Output Enable to Output Valid
Max
11
13.5
ns
t
CEZ
Chip Enable to High Z
Max
8
10
ns
t
OEZ
Output Enable to High Z
Max
8
10
ns
t
CES
CE# Setup Time to CLK
Min
4
5
ns
t
RDYS
RDY Setup Time to CLK
Min
4
5
ns
t
RACC
Ready Access Time from CLK
Max
11
13.5
ns
t
AAS
Address Setup Time to AVD# (Note 1)
Min
4
5
ns
t
AAH
Address Hold Time to AVD# (Note 1)
Min
6
7
ns
t
CAS
CE# Setup Time to AVD#
Min
0
ns
t
AVC
AVD# Low to CLK
Min
4
5
ns
t
AVD
AVD# Pulse
Min
10
12
ns
t
ACC
Access Time
Max
50
55
ns
t
CKA
CLK to access resume
Max
11
13.5
ns
t
CKZ
CLK to High Z
Max
8
10
ns
t
OES
Output Enable Setup Time
Min
4
5
ns
t
RCC
Read cycle for continuous suspend
Max
1
ms
相關(guān)PDF資料
PDF描述
AM49BDS640AHD8I Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
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相關(guān)代理商/技術(shù)參數(shù)
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AM49BDS640AHE8I 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write
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