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參數(shù)資料
| 型號： | AM49BDS640AH |
| 廠商： | Spansion Inc. |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | 堆疊多芯片封裝（MCP），閃存和1.8伏，只有同時讀/寫移動存儲芯片的CMOS |
| 文件頁數(shù)： | 16/84頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AM49BDS640AH |
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14
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
Handshake Burst Suspend/Resume at address 3Eh (or
offset from 3Eh),” on page 53, Figure 21, “Reduced
Wait-state Handshake Burst SuspendResume at
address 3Fh (or offset from 3Fh by a multiple of 64),” on
page 53, Figure 22, “Standard Handshake Burst
Suspend prior to Inital Access,” on page 54, Figure 23,
“Standard Handshake Burst Suspend at or after Inital
Access,” on page 54, Figure 24, “Standard Handshake
Burst Suspend at address 3Fh (starting address 3Dh
or earlier),” on page 55, Figure 25, “Standard Hand-
shake Burst Suspend at address 3Eh/3Fh (without a
valid Initial Access),” on page 55,
and
Figure 26, “Stan-
dard Handshake Burst Suspend at address 3Eh/3Fh
(with 1 Access CLK),” on page 56.
Burst plus Burst Suspend should not last longer than
t
RCC
without re-latching an address or crossing an
address boundary. To resume the burst access, OE#
must be re-asserted. The next active CLK edge will
resume the burst sequence where it had been sus-
pended. See
, Figure 27, “Read Cycle for Continuous
Suspend,” on page 56.
The RDY pin is only controlled by CE#. RDY will remain
active and is not placed into a high-impedance state
when OE# is de-asserted.
Configuration Register
The device uses a configuration register to set the
various burst parameters: number of wait states, burst
read mode, active clock edge, RDY configuration, and
synchronous mode active.
Reduced Wait-state Handshaking Option
The device can be equipped with a reduced wait-state
handshaking feature that allows the host system to
simply monitor the RDY signal from the device to deter-
mine when the initial word of burst data is ready to be
read. The host system should use the programmable
wait state configuration to set the number of wait states
for optimal burst mode operation. The initial word of
burst data is indicated by the rising edge of RDY after
OE# goes low.
The presence of the reduced wait-state handshaking
feature may be verified by writing the autoselect
command sequence to the device. See “Autoselect
Command Sequence” for details.
For optimal burst mode performance on devices
without the reduced wait-state handshaking option, the
host system must set the appropriate number of wait
states in the flash device depending on clock frequency
and the presence of a boundary crossing. See
“Set
Configuration Register Command Sequence” section
on page 26
section for more information. The device
will automatically delay RDY and data by one additional
clock cycle when the starting address is odd.
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank of
memory while programming or erasing in another bank
of memory. An erase operation may also be suspended
to read from or program to another location within the
same bank (except the sector being erased).
Figure 46, “Back-to-Back Read/Write Cycle Timings,”
on page 74
shows how read and write cycles may be
initiated for simultaneous operation with zero latency.
Refer to the DC Characteristics table for
read-while-program and read-while-erase current
specifications.
Writing Commands/Command Sequences
The device has the capability of performing an asyn-
chronous or synchronous write operation. While the
device is configured in Asynchronous read it is able to
perform Asynchronous write operations only. CLK is
ignored in the Asynchronous programming mode.
When in the Synchronous read mode configuration, the
device is able to perform both Asynchronous and Syn-
chronous write operations. CLK and WE# address
latch is supported in the Synchronous programming
mode. During a synchronous write operation, to write a
command or command sequence (which includes pro-
gramming data to the device and erasing sectors of
memory), the system must drive AVD# and CE# to V
IL
,
and OE# to V
IH
when providing an address to the
device, and drive WE# and CE# to V
IL
, and OE# to V
IH
when writing commands or data. During an asynchro-
nous write operation, the system must drive CE# and
WE# to V
IL
and OE# to V
IH
when providing an address,
command, and data. Addresses are latched on the last
falling edge of WE# or CE#, while data is latched on the
1st rising edge of WE# or CE#. The asynchronous and
synchronous programing operation is independent of
the Set Device Read Mode bit in the Configuration
Register (see
Table 14, “Configuration Register,” on
page 29
).
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word, instead of four.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table 10, “Sector Address
Table,” on page 27
indicates the address space that
each sector occupies. The device address space is
divided into four banks: Banks B and C contain only 32
Kword sectors, while Banks A and D contain both 4
Kword boot sectors in addition to 32 Kword sectors. A
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| AM49BDS640AHD9I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| AM49BDS640AHE8I | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
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