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AGR18030EF
30 W, 1.805 GHz—1.880 GHz, LDMOS RF Power Transistor
Introduction
The AGR18030EF is a high-voltage, gold-metallized,
laterally diffused metal oxide semiconductor
(LDMOS) RF power field effect transistor (FET) suit-
able for global system for mobile communication
(GSM), enhanced data for global evolution (EDGE),
and multicarrier class AB power amplifier applica-
tions. This device is manufactured using advanced
LDMOS technology offering state-of-the-art perfor-
mance and reliability. It is packaged in an industry-
standard package and is capable of delivering a min-
imum output power of 30 W, which makes it ideally
suited for today’s RF power amplifier applications.
Figure 1. Available (flanged) Packages
Features
Typical performance ratings for GSM EDGE
(f = 1.840 GHz, POUT = 10 W)
— Error vector magnitude (EVM): 1.6%
— Power gain: 15 dB
— Drain efficiency: 30%
— Modulation spectrum:
@ ±400 kHz = –64 dBc.
@ ±600 kHz = –71 dBc.
Typical continuous wave (CW) performance over
entire digital communication system (DCS) band:
— P1dB: 33 W typical (typ).
— Power gain: @ P1dB = 14 dB.
— Efficiency: @ P1dB = 51% typ.
— Return loss: –12 dB.
High-reliability, gold-metallization process.
Low hot carrier injection (HCI) induced bias drift
over 20 years.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
30 W minimum output power.
Device can withstand 10:1 voltage standing wave
ratio (VSWR) at 26 Vdc, 1.840 GHz, 30 W CW
output power.
Large signal impedance parameters available.
Table 1. Thermal Characteristics
Table 2. Absolute Maximum Ratings
*
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress rat-
ings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating
*
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations. Agere
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from elec-
trostatic charge. Reasonable precautions in han-
dling and packaging MOS devices should be
observed.
Parameter
Sym
Value
Unit
Thermal Resistance,
Junction to Case
R JC
2.0
°C/W
Parameter
Sym
Value
Unit
Drain-source Voltage
VDSS
65
Vdc
Gate-source Voltage
VGS –0.5, 15 Vdc
Drain Current Continuous
ID
Adc
Total Dissipation at TC = 25 °C PD
87.5
W
Derate Above 25 °C
—
0.5
W/°C
Operating Junction Tempera-
ture
TJ
200
°C
Storage Temperature Range TSTG –65, 150 °C
AGR18030EF
Minimum (V)
Class
HBM
500
1B
MM
50
A
CDM
1500
4
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