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參數(shù)資料
| 型號： | AGR21180EF |
| 廠商： | TRIQUINT SEMICONDUCTOR INC |
| 元件分類： | 功率晶體管 |
| 英文描述： | S BAND, Si, N-CHANNEL, RF POWER, MOSFET |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 355K |
| 代理商： | AGR21180EF |
AGR21180EF
180 W, 2.110 GHz—2.170 GHz, N-Channel E-Mode, Lateral MOSFET
Introduction
The AGR21180EF is a high-voltage, gold-metalized,
laterally diffused metal oxide semiconductor
(LDMOS) RF power transistor suitable for wideband
code division multiple access (W-CDMA), single and
multicarrier class AB wireless base station power
amplifier applications.
Figure 1. AGR21180EF (flanged) Package
Features
Typical performance for two carrier 3GPP
W-CDMA systems. F1 = 2135 MHz and
F2 = 2145 MHz with 3.84 MHz channel bandwidth
(BW), adjacent channel BW = 3.84 MHz at
F1 – 5 MHz and F2 + 5 MHz. Third-order distortion
is measured over 3.84 MHz BW at F1 – 10 MHz
and F2 + 10 MHz. Typical peak-to-average (P/A)
ratio of 8.5 dB at 0.01% (probability) CCDF:
— Output power: 38 W.
— Power gain: 14 dB.
— Efficiency: 26%.
— IM3: –36 dBc.
— ACPR: –39 dBc.
— Return loss: –12 dB.
High-reliability, gold-metalization process.
Hot carrier injection (HCI) induced bias drift of <5%
over 20 years.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
Device can withstand a 10:1 voltage standing wave
ratio (VSWR) at 28 Vdc, 2140 MHz, 180 W output
power pulsed 4 s at 10% duty.
Large signal impedance parameters available.
Table 1. Thermal Characteristics
Table 2. Absolute Maximum Ratings
*
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress rat-
ings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating
*
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations. Agere
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from elec-
trostatic charge. Reasonable precautions in han-
dling and packaging MOS devices should be
observed.
375D–03, STYLE 1
Parameter
Sym
Value
Unit
Thermal Resistance,
Junction to Case
R JC
0.35
°C/W
Parameter
Sym
Value
Unit
Drain-source Voltage
VDSS
65
Vdc
Gate-source Voltage
VGS –0.5, 15 Vdc
Total Dissipation at TC = 25 °C PD
500
W
Derate Above 25 ˇC
—
2.86 W/°C
Operating Junction Tempera-
ture
TJ
200
°C
Storage Temperature Range TSTG –65, 150 °C
AGR21180EF
Minimum (V)
Class
HBM
500
1B
MM
50
A
CDM
1000
4
PEAK Devices
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