參數資料
| 型號： | ADV7194KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 4/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER VIDEO EXT-10 80-LQFP |
| 標準包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應用： | DVD，視頻，多媒體 |
| 電壓 - 電源，模擬： | 3.3 V ~ 5 V |
| 電壓 - 電源，數字： | 3.3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產品目錄頁面： | 788 (CN2011-ZH PDF) |
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ADV7194
–12–
REV. A
The output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts
(and can generate)
HSYNC, VSYNC and FIELD timing sig-
nals. These timing signals can be adjusted to change pulsewidth
and position while the part is in master mode.
HSO/CSO and VSO TTL outputs are also available and are
timed to the analog output video.
A separate teletext port enables the user to directly input teletext
data during the vertical blanking interval.
The ADV7194 also incorporates WSS and CGMS-A data control
generation.
The ADV7194 modes are set up over a 2-wire serial bidirectional
port (I
2C-compatible) with two slave addresses and the device is
register-compatible with the ADV7172/ADV7173.
The ADV7194 is packaged in an 80-lead LQFP package.
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, N, and NTSC M, N modes, YCrCb
4:2:2 Data is input via the CCIR-656/601-compatible Pixel Port at
a 27 MHz Data Rate. The Pixel Data is demultiplexed to form
three data paths. Y typically has a range of 16 to 235, Cr and Cb
typically have a range of 128+/–112; however, it is possible to input
data from 1 to 254 on both Y, Cb, and Cr. The ADV7194 sup-
ports PAL (B, D, G, H, I, N) and NTSC M, N (with and without
Pedestal) and PAL60 standards.
Digital Noise Reduction can be applied to the Y signal. Pro-
grammable gamma correction can also be applied to the Y
signal if required.
The Y data can be manipulated for contrast control and a setup
level can be added for brightness control. The Cr, Cb data can
be scaled to achieve color saturation control. All settings become
effective at the start of the next eld when double buffering is
enabled.
The appropriate sync, blank and burst levels are added to the
YCrCb data. Closed-Captioning and Teletext levels are also
added to Y and the resultant data is interpolated to 54 MHz
(4
× Oversampling Mode). The interpolated data is ltered and
scaled by three digital FIR lters.
The U and V signals are modulated by the appropriate Subcarrier
Sine/Cosine waveforms and a phase offset may be added onto the
color subcarrier during active video to allow hue adjustment. The
resulting U and V signals are added together to make up the
Chrominance Signal. The Luma (Y) signal can be delayed by up
to six clock cycles (at 27 MHz) and the Chroma signal can be
delayed by up to eight clock cycles (at 27 MHz).
The Luma and Chroma signals are added together to make up
the Composite Video Signal. All timing signals are controlled.
The YCrCb data is also used to generate RGB data with appropri-
ate sync and blank levels. The YUV levels are scaled to output the
suitable SMPTE/EBU N10, MII, or Betacam levels.
Each DAC can be individually powered off if not required. A
complete description of DAC output congurations is given in
the Mode Register 2 section.
Video output levels are illustrated in Appendix 9.
Digital noise reduction allows improved picture quality in
removing low-amplitude, high-frequency noise. Figure 6 shows
the DNR functionality in the two modes available.
Programmable gamma correction is also available. The figure
below shows the response of different gamma values to a ramp
input signal.
250
200
150
100
50
0
300
SIGNAL OUTPUTS
SIGNAL
INPUT
0.5
GAMMA CORRECTION BLOCK OUTPUT
TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA-CORRECTED
AMPLITUDE
0
50
100
150
200
250
LOCATION
0.3
1.5
1.8
Figure 7. Signal Input (Ramp) and Selectable Gamma
Output Curves
The device is driven by a 27 MHz clock. Data can be output at
27 MHz or 54 MHz (on-board PLL) when 4
× oversampling is
enabled. Also, the filter requirements in 4
× oversampling and 2×
oversampling differ, as can be seen in the figure below.
–30dB
0dB
6.75MHz
13.5MHz
27.0MHz
40.5MHz
54.0MHz
2
FILTER
REQUIREMENTS
4
FILTER
REQUIREMENTS
Figure 8. Output Filter Requirements in 2
× and 4×
Oversampling Mode
ENCODER
CORE
2
I
N
T
E
R
P
O
L
A
T
I
O
N
6
D
A
C
O
U
T
P
U
T
S
54MHz
OUTPUT
RATE
ADV7194
PLL
54MHz
MPEG2
PIXEL BUS
27MHz
Figure 9. PLL and 4x Oversampling Block Diagram
The ADV7194 also supports both PAL and NTSC square pixel
operation. In this case, the encoder requires a 24.5454 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
An advanced power management circuit enables optimal con-
trol of power consumption in both normal operating modes or
sleep modes.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
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