- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1901 > ADV7194KSTZ (Analog Devices Inc)IC ENCODER VIDEO EXT-10 80-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADV7194KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ENCODER VIDEO EXT-10 80-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | DVD，視頻，多媒體 |
| 電壓 - 電源，模擬： | 3.3 V ~ 5 V |
| 電壓 - 電源，數(shù)字： | 3.3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
ADV7194
–32–
REV. A
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4–SR0) = 03H)
Mode Register 3 is an 8-bit-wide register. Figure 58 shows
the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30–MR31)
This bit is read only and indicates the revision of the device.
VBI_Open (MR32)
This bit determines whether or not data in the Vertical Blanking
Interval (VBI) is output to the analog outputs or blanked. Note
that this condition is also valid in Timing Slave Mode 0. For
further information see Vertical Blanking section.
Teletext Enable (MR33)
This bit must be set to 1 to enable teletext data insertion on
the TTX pin. Note: TTX functionality is shared with
VSO and
CLAMP on Pin 62. CLAMP/
VSO Select (MR77) and TTX
Input/CLAMP/
VSO Output (MR76) have to be set accordingly.
Teletext Bit Request Mode Control (MR34)
This bit enables switching of the teletext request signal from a
continuous high signal (MR34 = 0) to a bitwise request signal
(MR34 = 1).
Closed Captioning Field Control (MR35–MR36)
These bits control the elds that closed captioning data is dis-
played on, closed captioning information can be displayed on
an odd eld, even eld or both elds.
Reserved (MR37)
A Logic 0 must be written to this bit.
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Mode Register 4 is an 8-bit-wide register. Figure 59 shows
the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
VSYNC_3H Control (MR40)
When this bit is enabled (1) in Slave Mode, it is possible to
drive the
VSYNC input low for 2.5 lines in PAL mode and
three lines in NTSC mode. When this bit is enabled in Master
Mode the ADV7194 outputs an active low
VSYNC signal for
three lines in NTSC mode and 2.5 lines in PAL mode.
Genlock Control (MR41–MR42)
These bits control the Genlock feature and timing reset of the
ADV7194 Setting MR41 and MR42 to Logic 0 disables the
SCRESET/RTC/TR pin and allows the ADV7194 to operate in
normal mode.
1. By setting MR41 to zero and MR42 to one, a timing reset is
applied, resetting the horizontal and vertical counters. This
has the effect of resetting the Field Count to Field 0.
If the SCRESET/RTC/TR pin is held high, the counters
will remain reset. Once the pin is released the counters will
commence counting again. For correct counter reset, the
SCRESET/RTC/TR pin has to remain high for at least
37 ns (one clock cycle at 27 MHz).
2. If MR41 is set to one and MR42 is set to zero, the SCRESET/
RTC/TR pin is congured as a subcarrier reset input and
the subcarrier phase will reset to Field 0 whenever a low-to-
high transition is detected on the SCRESET/RTC/TR pin
(SCH phase resets at the start of the next eld).
3. If MR41 is set to one and MR42 is set to one, the SCRESET/
RTC/TR pin is congured as a real time control input and
the ADV7194 can be used to lock to an external video source
working in RTC mode. See Figure 37.
Active Video Line Duration Control (MR43)
This bit switches between two active video line durations. A zero
selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one
selects ITU-R BT. 470 standard for active video duration (710
pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)
This bit enables the color information to be switched on and off
the chroma, color component, composite video outputs.
Burst Control (MR45)
This bit enables the color burst to be switched on and off the
chroma and composite video outputs.
Color Bar Control (MR46)
This bit can be used to generate and output an internal color
bar test pattern. The color bar conguration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7194 is congured in a
Master Timing mode. The output pins
VSYNC, HSYNC and
BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninterlaced
mode.
MR37
ZERO MUST BE
WRITTEN TO
THIS BIT
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR31 MR30
RESERVED FOR
REVISION CODE
VBI OPEN
0
DISABLE
1
ENABLE
MR32
TTX BIT REQUEST
MODE CONTROL
0
DISABLE
1
ENABLE
MR34
TELETEXT
ENABLE
0
DISABLE
1
ENABLE
MR33
CLOSED CAPTIONING
FIELD CONTROL
MR36 MR35
0
NO DATA OUT
0
1
ODD FIELD ONLY
1
0
EVEN FIELD ONLY
1
DATA OUT
(BOTH FIELDS)
Figure 58. Mode Register 3, MR3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7202KSTZ | IC CODEC VIDEO 10BIT 64LQFP |
| ADV7311KST | IC VID ENC 6-12BIT DAC'S 64LQFP |
| ADV7321KSTZ | IC VID ENC 6-12BIT DAC'S 64LQFP |
| ADV7343BSTZ | IC ENCODER VIDEO W/DAC 64-LQFP |
| ADV7391BCPZ | IC ENCODER VIDEO W/DAC 32LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。