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參數(shù)資料
| 型號(hào)： | ADV7194KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/69頁 |
| 文件大小： | 0K |
| 描述： | IC ENCODER VIDEO EXT-10 80-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | DVD，視頻，多媒體 |
| 電壓 - 電源，模擬： | 3.3 V ~ 5 V |
| 電壓 - 電源，數(shù)字： | 3.3 V ~ 5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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ADV7194
–20–
REV. A
YUV LEVELS
This functionality allows the ADV7194 to output SMPTE levels
or Betacam levels on the Y output when congured in PAL or
NTSC mode.
Sync
Video
Betacam
286 mV
714 mV
SMPTE
300 mV
700 mV
MII
300 mV
700 mV
As the data path is branched at the output of the lters the luma
signal relating to the CVBS or S-Video Y/C output is unaltered.
It is only the Y output of the YCrCb outputs that is scaled.
This control allows color component levels to have a peak-peak
amplitude of 700 mV, 1000 mV or the default values of 934 mV
in NTSC and 700 mV in PAL. (Mode Register 5.)
20-/16-BIT INTERFACE
It is possible to input data in 20-bit or 16-bit format. In this
case, the interface only operates if the data is accompanied by
separate
HSYNC/VSYNC/BLANK signals. Twenty-bit or 16-
bit mode is not available in Slave Mode 0 since EAV/SAV timing
codes are used. (Mode Register 8.)
4
OVERSAMPLING AND INTERNAL PLL
It is possible to operate all six DACs at 27 MHz (2
× Oversam-
pling) or 54 MHz (4
× Oversampling).
The ADV7194 is supplied with a 27 MHz clock synced with the
incoming data. Two options are available: to run the device
throughout at 27 MHz or to enable the PLL. In the latter case,
even if the incoming data runs at 27 MHz, 4
× Oversampling
and the internal PLL will output the data at 54 MHz.
NOTE
In 4
× Oversampling Mode the requirements for the optional
output lters are different than from those in 2
× Oversampling.
(Mode Register 1, Mode Register 6.)
27MHz
54MHz
OUTPUT
PLL
I
N
T
E
R
P
O
L
A
T
I
O
N
2
54MHz
6
D
A
C
O
U
T
P
U
T
S
ADV7194
PIXEL BUS
ENCODER
CORE
MPEG2
Figure 35a. PLL and 4
× Oversampling Block Diagram
–30dB
0dB
6.75MHz
13.5MHz
27.0MHz
40.5MHz
54.0MHz
2
FILTER
REQUIREMENTS
4
FILTER
REQUIREMENTS
Figure 35b. Output Filter Requirements in 4
× Oversam-
pling Mode
VIDEO TIMING DESCRIPTION
The ADV7194 is intended to interface to off-the-shelf MPEG1
and MPEG2 Decoders. As a consequence, the ADV7194 accepts
4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has
several Video Timing Modes of operation that allow it to be
congured as either System Master Video Timing Generator or
a Slave to the System Video Timing Generator. The ADV7194
generates all of the required horizontal and vertical timing periods
and levels for the analog video outputs.
The ADV7194 calculates the width and placement of analog sync
pulses, blanking levels, and color burst envelopes. Color bursts
are disabled on appropriate lines and serration and equalization
pulses are inserted where required.
In addition, the ADV7194 supports a PAL or NTSC square pixel
operation. The part requires an input pixel clock of 24.5454 MHz
for NTSC square pixel operation and an input pixel clock of
29.5 MHz for PAL square pixel operation. The internal hori-
zontal line counters place the various video waveform sections in
the correct location for the new clock frequencies.
The ADV7194 has four distinct Master and four distinct Slave
timing congurations. Timing Control is established with the
bidirectional
HSYNC, BLANK and VSYNC pins. Timing Regis-
ter 1 can also be used to vary the timing pulsewidths and where
they occur in relation to each other. (Mode Register 2, Timing
Register 0, 1.)
RESET SEQUENCE
When
RESET becomes active the ADV7194 reverts to the
default output conguration (see Appendix for register settings).
The ADV7194 internal timing is under the control of the logic
level on the NTSC_PAL pin.
When
RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7194. Output timing signals
are still suppressed at this stage. DACs A, B, C are switched off
and DACs D, E, F are switched on.
When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
the encoder. Digital output timing signals become active and
the encoder timing is now under the control of the Timing Regis-
ters. If at this stage, the user wishes to select a different video
standard to that on the NTSC_PAL pin, Standard I
2C Con-
trol should be enabled (MR25 = 1) and the video standard
required is selected by programming Mode Register 0 (Out-
put Video Standard Selection). Figure 36 illustrates the
RESET
sequence timing.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7194KSTZ | 制造商:Analog Devices 功能描述:TV / Video IC |
| ADV7195 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk |
| ADV7195KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input |
| ADV7195KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP |
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