參數(shù)資料
型號(hào)： ADV7177KSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/44頁(yè)
文件大?。?/td> 0K
描述： IC DAC VIDEO NTSC 3-CH 44MQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 800
類(lèi)型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，電視
電壓 - 電源，模擬： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7177/ADV7178
Rev. C | Page 30 of 44
TIMING REGISTER 1 (TR17–TR10)
Address [SR4–SR0] = 0CH
Timing Register 1 is an 8-bit-wide register. Figure 38 shows the
various operations under the control of Timing Register 1. This
register can be read from as well as written to. This register can
be used to adjust the width and position of the master mode
timing signals.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulse width.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)
When the device is in Timing Mode 1, these bits adjust the
position of the HSYNC output relative to the FIELD output
rising edge.
VSYNC Width (TR15–TR14)
When the ADV7177/ADV7178 are in Timing Mode 2, these
bits adjust the VSYNC pulse width.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the pixel
data and allows the Cr and Cb components to be swapped. This
adjustment is available in both master and slave timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
Address [SR4-SR0] = 0DH
Mode Register 2 is an 8-bit-wide register. Figure 39 shows the
various operations under the control of Mode Register 2. This
register can be read from as well as written to.
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC WIDTH
TR11
0
1
TR10
0
1
0
1
TA
1× TPCLK
4× TPCLK
16 × TPCLK
128 × TPCLK
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
TR15
X
x
TR14
0
1
TC
TB
TB + 32s
HSYNC TO PIXEL
DATA ADJUST
TR17
0
1
TR16
0
1
0
1
0 3 TPCLK
1 3 TPCLK
2 3 TPCLK
3 3 TPCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15
0
1
TR14
0
1
0
1
1× TPCLK
4× TPCLK
16 × TPCLK
128 × TPCLK
LINE 313
LINE 314
LINE 1
TIMING MODE 1 (MASTER/PAL)
HSYNC
FIELD/VSYNC
HSYNC TO
FIELD/VSYNC DELAY
TR13
0
1
TR12
0
1
0
1
TB
0× TPCLK
4× TPCLK
8× TPCLK
16 × TPCLK
TA
TB
TC
00228-038
Figure 38. Timing Register 1
MR21
MR27
MR22
MR23
MR26
MR25
MR24
MR20
CHROMINANCE
CONTROL
ENABLE COLOR
DISABLE COLOR
MR24
0
1
RGB/YUV
CONTROL
RGB OUTPUT
YUV OUTPUT
MR26
0
1
SQUARE PIXEL
CONTROL
DISABLE
ENABLE
MR20
0
1
BURST
CONTROL
ENABLE BURST
DISABLE BURST
MR25
0
1
ACTIVE VIDEO
LINE DURATION
MR23
0
1
MR22–MR21
(00)
ZERO SHOULD
BE WRITTEN TO
THESE BITS
LOW POWER
MODE
DISABLE
ENABLE
MR27
0
1
720 PIXELS
710 PIXELS/702 PIXELS
00228-039
Figure 39. Mode Register 2
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