參數(shù)資料
型號(hào)： ADV7177KSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/44頁(yè)
文件大?。?/td> 0K
描述： IC DAC VIDEO NTSC 3-CH 44MQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 800
類(lèi)型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，電視
電壓 - 電源，模擬： 3 V ~ 3.6 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7177/ADV7178
Rev. C | Page 23 of 44
Mode 2: Master Option HSYNC, VSYNC, BLANK
Timing Register 0 TR0 = X X X X X 1 0 1
In this mode, the ADV7177/ADV7178 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7177/ADV7178 automatically blank all normally blank lines
as per the BT-470 specification. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illustrates the HSYNC, BLANK,
and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the HSYNC, BLANK, and VSYNC for an
odd-to-even field transition relative to the pixel data.
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
HSYNC
VSYNC
BLANK
PIXEL
DATA
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
Cb
Y
Cr
00228-023
Figure 23. Timing Mode 2, Even-to-Odd Field Transition, Master/Slave
HSYNC
VSYNC
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
PAL = 864
× CLOCK/2
NTSC = 858
× CLOCK/2
00228-024
Figure 24. Timing Mode 2, Odd-to-Even Field Transition, Master/Slave
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