參數(shù)資料
型號(hào)： ADV7177KSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 21/44頁
文件大?。?/td> 0K
描述： IC DAC VIDEO NTSC 3-CH 44MQFP
產(chǎn)品變化通告： ADV7xxx Obsolescence 16/Jan/2012
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，電視
電壓 - 電源，模擬： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7177/ADV7178
Rev. C | Page 28 of 44
MR01
MR00
MR07
MR02
MR04
MR03
MR05
MR06
OUTPUT VIDEO
STANDARD SELECTION
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
MR01
0
1
MR00
0
1
0
1
MR07
ZERO SHOULD
BE WRITTEN TO
THIS BIT
OUTPUT SELECT
YC OUTPUT
RGB/YUV OUTPUT
MR06
0
1
LUMINANCE FILTER CONTROL
LOW-PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW-PASS FILTER (B)
MR04
0
1
MR03
0
1
0
1
RGB SYNC
DISABLE
ENABLE
MR05
0
1
PEDESTAL CONTROL
PEDESTAL OFF
PEDESTAL ON
MR02
0
1
00228-032
Figure 32. Mode Register 0 (MR0)
MR11
MR10
MR17
MR12
MR13
MR15
MR16
MR14
CLOSED CAPTIONING
FIELD SELECTION
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
MR12
0
1
MR11
0
1
0
1
MR16
ONE SHOULD
BE WRITTEN TO
THIS BIT
LUMA
DAC CONTROL
CHROMA
DAC CONTROL
COMPOSITE
DAC CONTROL
MR15
0
1
INTERLACED MODE
CONTROL
INTERLACED
NONINTERLACED
MR10
0
1
COLOR BAR
CONTROL
DISABLE
ENABLE
MR17
0
1
MR14
0
1
NORMAL
POWER-DOWN
NORMAL
POWER-DOWN
MR13
0
1
NORMAL
POWER-DOWN
00228-033
Figure 33. Mode Register 1 (MR1)
Output Select (MR06)
This bit specifies if the part is in composite video or RGB/YUV
mode. Note that the main composite signal is still available in
RGB/YUV mode.
MODE REGISTER 1 MR1 (MR17–MR10)
Address (SR4–SR0) = 01H
Figure 33 shows the various operations under the control of
Mode Register 1. This register can be read from as well as
written to.
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is relevant only when the part is in
composite video mode.
Closed Captioning Field Selection (MR12–MR11)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field, or both fields.
DAC Control (MR15–MR13)
These bits can be used to power down the DACs to reduce the
power consumption of the ADV7177/ADV7178 if any of the
DACs are not required in the application.
Color Bar Control (MR17)
This bit can be used to generate and output an internal color-
bar test pattern. The color-bar configuration is 100/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. Note that when color bars
are enabled, the ADV7177/ADV7178 are configured in a master
timing mode as per the one selected by bits TR01 and TR02.
SUBCARRIER FREQUENCY REGISTER 3–0
FSC3–FSC0
Address [SR4–SR0] = 05H–02H
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using the
following equation, in which the asterisk (*) means rounded to
the nearest integer:
*
2
27
.
32
×
Line
Video
One
in
Cycles
Clock
MHz
of
No
Line
Video
of
Line
One
in
Values
Frequency
Subcarrier
of
No
For example, in NTSC mode
Fh
1
C
07
F
21
569408542
2
1716
5
.
227
32
=
×
=
d
Value
Frequency
Subcarrier
Note that on power-up, FSC Register 0 is set to 16h. A value of
1F as derived above is recommended.
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