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| 型號： | ADV7177KSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO NTSC 3-CH 44MQFP |
| 產(chǎn)品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | 機頂盒，電視 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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ADV7177/ADV7178
Rev. C | Page 10 of 44
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V,1 VREF = 1.235 V, RSET = 300 . All specifications TMIN to TMAX,2 unless otherwise noted.
Table 6.
Parameter
Conditions
Min
Typ
Max
Unit
MPU PORT3, 4
SCLOCK Frequency
0
100
kHz
SCLOCK High Pulse Width, t1
4.0
s
SCLOCK Low Pulse Width, t2
4.7
s
Hold Time (Start Condition), t3
After this period the first clock is generated
4.0
s
Setup Time (Start Condition), t4
Repeated for start condition
4.7
s
Data Setup Time, t5
250
ns
SDATA, SCLOCK Rise Time, t6
1
s
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
4.7
s
ANALOG OUTPUTS3, 5
Analog Output Delay
7
ns
DAC Analog Output Skew
0
ns
CLOCK CONTROL AND PIXEL PORT3, 4, 6
fCLOCK
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
3.5
ns
Data Hold Time, t12
4
ns
Control Setup Time, t11
4
ns
Control Hold Time, t12
3
ns
Digital Output Access Time, t13
24
ns
Digital Output Hold Time, t14
4
ns
Pipeline Delay, t15
37
Clock cycles
RESET CONTROL3, 4
RESET Low Time
6
ns
INTERNAL CLOCK CONTROL
Clock/2 Rise Time, t16
10
ns
Clock/2 Fall Time, t17
10
ns
OSD TIMING4
OSD Setup Time, t18
10
ns
OSD Hold Time, t19
2
ns
1 The max/min specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: 0°C to 70°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load
≤ 10 pF.
4 Guaranteed by characterization.
5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 Pixel port consists of the following:
Pixel inputs: P15–P0
Pixel controls: HSYNC, FIELD/VSYNC, BLANK
Clock input: CLOCK
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