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參數(shù)資料
| 型號： | ADV7177KSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO NTSC 3-CH 44MQFP |
| 產(chǎn)品變化通告： | ADV7xxx Obsolescence 16/Jan/2012 |
| 標準包裝： | 800 |
| 類型： | 視頻編碼器 |
| 應用： | 機頂盒，電視 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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ADV7177/ADV7178
Rev. C | Page 29 of 44
Program as
FSC Register 0: 1Fh
FSC Register 2: 7Ch
FSC Register 3: F0h
FSC Register 4: 21h
Figure 34 shows how the frequency is set up by the four
registers.
SUBCARRIER
FREQUENCY
REG 3
SUBCARRIER
FREQUENCY
REG 2
SUBCARRIER
FREQUENCY
REG 1
SUBCARRIER
FREQUENCY
REG 0
FSC30
FSC29
FSC27
FSC25
FSC28
FSC24
FSC31
FSC26
FSC22
FSC21
FSC19
FSC17
FSC20
FSC16
FSC23
FSC18
FSC14
FSC13
FSC11
FSC9
FSC12
FSC8
FSC15
FSC10
FSC6
FSC5
FSC3
FSC1
FSC4
FSC0
FSC7
FSC2
00228-067
Figure 34. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER (FP7–FP0)
Address [SR4–SR0] = 06H
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41 degrees.
TIMING REGISTER 0 (TR07–TR00)
Address [SR4–SR0] = 07H
Figure 37 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR0 BIT DESCRIPTION
Master/Slave Control (TR00)
This bit controls whether the ADV7177/ADV7178 are in master
or slave mode. This register can be used to adjust the width and
position of the master timing signals.
Timing Mode Selection (TR02–TR01)
These bits control the timing mode of the ADV7177/ADV7178.
These modes are described in the Timing and Control section.
Input Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
Luma Delay (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
Pixel Port Control (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected, the data is set up on
Pins P7–P0.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the
internal timing counters. This bit should be toggled after
power-up, reset, or after changing to a new timing mode.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED0)
Address [SR4–SR0] = 09H–08H
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 35
shows how the high and low bytes are set up in the registers.
BYTE 0
CED6
CED5
CED3
CED1
CED4
CED2
CED0
CED7
CED14 CED13
CED11
CED9
CED12
CED10
CED8
CED15
00228-036
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
Subaddress [SR4–SR0] = 0BH–0AH
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 36 shows how
the high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CCD6
CCD5
CCD3
CCD1
CCD4
CCD2
CCD0
CCD7
CCD14 CCD13
CCD11
CCD9
CCD12
CCD10
CCD8
CCD15
00228-037
Figure 36. Closed Captioning Data Register
TR01
TR00
TR07
TR02
TR03
TR05
TR06
TR04
TIMING
REGISTER RESET
TR07
BLANK INPUT
CONTROL
ENABLE
DISABLE
TR03
0
1
PIXEL PORT
CONTROL
8-BIT
16-BIT
TR06
0
1
MASTER/SLAVE
CONTROL
SLAVE TIMING
MASTER TIMING
TR00
0
1
LUMA DELAY
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
TR05
0
1
TR04
0
1
0
1
TIMING MODE
SELECTION
MODE 0
MODE 1
MODE 2
MODE 3
TR02
0
1
TR01
0
1
0
1
00228-035
Figure 37. Timing Register 0
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