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參數(shù)資料
型號(hào)： ADV7171KSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 38/64頁
文件大?。?/td> 0K
描述： IC DAC VIDEO ENC NTSC 44-MQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7170/ADV7171
Rev. C | Page 43 of 64
APPENDIX 5—TELETEXT INSERTION
The tPD is the time needed by the ADV7170/ADV7171 to
interpolate input data on TTX and insert it onto the CVBS
or Y outputs, such that it appears tSYNTTXOUT = 10.2 μs after the
leading edge of the horizontal signal. Time TTXDEL is the
pipeline delay time by the source that is gated by the TTXREQ
signal in order to deliver TTX data.
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 μs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable
pipeline delays.
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext Standard
of PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/sec;
this is achieved by setting TC03 to TC00 to 0. The insertion
window is not open if the teletext enable bit (MR35) is set to 0.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is as follows:
(27 MHz/4) = 6.75 MHz
(6.9375 × 106/6.75 × 106) = 1.027777
Thus, 37 TTX bits correspond to 144 clocks (27 MHz), and
each bit has a width of nearly four clock cycles. The ADV7170/
ADV7171 use an internal sequencer and variable phase
interpolation filter to minimize the phase jitter and thus
generate a bandlimited signal that can be output on the CVBS
and Y outputs.
At the TTX input, the bit duration scheme repeats after every 37
TTX bits or 144 clock cycles. The protocol requires that TTX
Bit 10, Bit 19, Bit 28, and Bit 37 are carried by three clock cycles;
all other bits are carried by four clock cycles. After 37 TTX bits,
the next bits with three clock cycles are Bit 47, Bit 56, Bit 65,
and Bit 74. This scheme holds for all following cycles of 37 TTX
bits, until all 360 TTX bits are completed. All teletext lines are
implemented in the same way. Individual control of teletext
lines is controlled by teletext setup registers.
ADDRESS AND DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
00221-059
Figure 59. Teletext VBI Line
PROGRAMMABLE PULSE EDGES
tPD
CVBS/Y
HSYNC
TTXREQ
TTXDATA
tSYNTTXOUT
10.2
μs
TTXDEL
TTXST
tSYNTTXOUT = 10.2μs
tPD = PIPELINE DELAY THROUGH ADV7170/ADV7171
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
00221-060
Figure 60. Teletext Functionality Diagram
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