參數資料
型號： ADV7171KSZ-REEL
廠商： Analog Devices Inc
文件頁數： 29/64頁
文件大?。?/td> 0K
描述： IC DAC VIDEO ENC NTSC 44-MQFP
產品變化通告： Product Discontinuance 27/Oct/2011
標準包裝： 800
類型： 視頻編碼器
應用： 機頂盒，視頻播放器
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應商設備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7170/ADV7171
Rev. C | Page 35 of 64
TR11
TR10
TR17
TR12
TR13
TR15
TR16
TR14
HSYNC TO PIXEL
DATA ADJUST
TR17 TR16
00
0
× T
PCLK
01
1
× T
PCLK
10
2
× T
PCLK
11
3
× T
PCLK
HSYNC TO
FIELD/VSYNC DELAY
TR13 TR12
00
0
× T
PCLK
01
4
× T
PCLK
10
8
× T
PCLK
11
16
× T
PCLK
TB
HSYNC WIDTH
00
1
× T
PCLK
01
4
× T
PCLK
10
16
× T
PCLK
1
128
× T
PCLK
TR11 TR10
TA
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
x0
TB
x1
TB + 32μs
TR15 TR14
TC
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
00
1
× T
PCLK
01
4
× T
PCLK
10
16
× T
PCLK
1
128
× T
PCLK
LINE 313
LINE 314
LINE 1
TB
TIMING MODE 1 (MASTER/PAL)
FIELD/VSYNC
TC
TA
HSYNC
00221-
044
Figure 44. Timing Register 1
SUBCARRIER FREQUENCY REGISTERS 0 TO 3
(FSC3 TO FSC0)
(Address [SR4 to SR00] = 09H to 0CH)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using
the following equation, rounded to the nearest integer:
32
2
27
.
×
Line
Video
One
in
Cycles
Clock
MHz
of
No
Line
Video
of
Line
One
in
Values
Frequency
Subcarrier
of
No
For example, in NTSC mode,
Fh
C
F
d
alue
V
Frequency
Subcarrier
1
07
21
569408542
2
1716
5
.
227
32
=
×
=
Note that on power-up, FSC Register 0 is set to 16h. A value of 1F
as derived above is recommended.
Program as follows:
FSC Register 0: 1FH
FSC Register 2: 7CH
FSC Register 3: F0H
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 3
FSC30
FSC29
FSC27
FSC25
FSC28
FSC24
FSC31
FSC26
SUBCARRIER
FREQUENCY
REG 2
FSC22
FSC21
FSC19
FSC17
FSC20
FSC16
FSC23
FSC18
SUBCARRIER
FREQUENCY
REG 1
FSC14 FSC13
FSC11
FSC9
FSC12
FSC8
FSC15
FSC10
SUBCARRIER
FREQUENCY
REG 0
FSC6
FSC5
FSC3
FSC1
FSC4
FSC0
FSC7
FSC2
00221-
045
Figure 45. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTERS (FP7 TO FP0)
(Address [SR4 to SR0] = 0DH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
CLOSED CAPTIONING EVEN FIELD DATA
REGISTER 1 TO 0 (CED15 TO CED0)
(Address [SR4–SR0] = 0E to 0FH)
These 8-bit-wide registers are used to set up the closed
captioning extended data bytes on even fields. Figure 46
shows how the high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CED6
CED5
CED3
CED1
CED4
CED2
CED0
CED7
CED14 CED13
CED11
CED9
CED12
CED10
CED8
CED15
00221-046
Figure 46. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD DATA
REGISTERS 1 TO 0 (CCD15 TO CCD0)
(Subaddress [SR4 to SR0] = 10H to 11H)
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
BYTE 1
BYTE 0
CCD6
CCD5
CCD3
CCD1
CCD4
CCD2
CCD0
CCD7
CCD14 CCD13
CCD11
CCD9
CCD12
CCD10
CCD8
CCD15
00221-047
Figure 47. Closed Captioning Data Register
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