參數(shù)資料
型號(hào)： ADV7171KSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 17/64頁
文件大?。?/td> 0K
描述： IC DAC VIDEO ENC NTSC 44-MQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7170/ADV7171
Rev. C | Page 24 of 64
622
623
624
625
1
2
3
4
5
67
21
22
23
DISPLAY
ODD FIELD
EVEN FIELD
HSYNC
BLANK
VSYNC
DISPLAY
309
310
311
312
313
314
315
316
317
318
319
334
335
336
DISPLAY
ODD FIELD
EVEN FIELD
HSYNC
BLANK
DISPLAY
320
VSYNC
VERTICAL BLANK
00221-
028
Figure 28. Timing Mode 2 (PAL)
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as
per CCIR-624. Mode 2 is shown in
(NTSC) and
(PAL).
shows the
HSYNC, BLANK, and VSYNC for an
even-to-odd field transition relative to the pixel data.
shows the
HSYNC, BLANK, and VSYNC for an odd-to-even field
transition relative to the pixel data.
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
HSYNC
VSYNC
PIXEL
DATA
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
Cb
Y
Cr
Y
BLANK
00221-029
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
PAL = 864
× CLOCK/2
NTSC = 858
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
HSYNC
VSYNC
PIXEL
DATA
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
Cb
Y
Cr
Y
Cb
BLANK
00221-030
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
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