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參數(shù)資料
| 型號： | ADV7171KSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO ENC NTSC 44-MQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | 機(jī)頂盒，視頻播放器 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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ADV7170/ADV7171
Rev. C | Page 30 of 64
MR01
MR00
MR07
MR02
MR03
MR05
MR06
MR04
MR07
MR06
MR05
000
001
010
011
100
101
110
111
1.3MHz LOW PASS FILTER
0.65MHz LOW PASS FILTER
1.0MHz LOW PASS FILTER
2.0MHz LOW PASS FILTER
RESERVED
CIF
Q CIF
RESERVED
CHROMA FILTER SELECT
MR04
MR03
MR02
00
0
00
1
01
0
00
1
10
0
10
1
11
0
11
1
LOW PASS FILTER (NTSC)
LOW PASS FILTER (PAL)
NOTCH FILTER (NTSC)
NOTCH FILTER (PAL)
EXTENDED MODE
CIF
Q CIF
RESERVED
LUMA FILTER SELECT
MR01
MR00
00
01
10
11
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
OUTPUT VIDEO
STANDARD SELECTION
00221-038
Figure 38. Mode Register 0
Color Bar Control (MR17)
MODE REGISTER 1 MR1 (MR17 TO MR10)
This bit can be used to generate and output an internal color bar
test pattern. The color bar configuration is 100/7.5/75/7.5 for
NTSC and 100/0/75/0 for PAL. It is important to note that when
color bars are enabled, the ADV7170/ADV7171 are configured
in a master timing mode.
(Address (SR4 to SR0) = 01H)
Figure 39 shows the various operations under the control of
Mode Register 1. This register can be read from as well as
written to.
MR1 BIT DESCRIPTION
MODE REGISTER 2 MR2 (MR27 TO MR20)
Interlace Control (MR10)
(Address [SR4 to SR0] = 02H)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
Mode Register 2 is an 8-bit-wide register.
Figure 40 shows the various operations under the control of
Mode Register 2. This register can be read from as well as
written to.
Closed Captioning Field Selection (MR12 to MR11)
These bits control the fields on which closed captioning data is
displayed. Closed captioning information can be displayed on
an odd field, even field, or both odd and even fields.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
DAC Control (MR16 to MR13)
These bits can be used to power down the DACs. This can be
used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the
application.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7171SU | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
| ADV7171WBSZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder |
| ADV7172 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7172KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7172KST-REEL | 制造商:Analog Devices 功能描述: |
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