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| 型號： | ADV7171KSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VIDEO ENC NTSC 44-MQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | 機頂盒，視頻播放器 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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ADV7170/ADV7171
Rev. C | Page 11 of 64
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
44
CLOCK
43
GND
42
P4
41
P3
40
P2
39
P1
38
P0
37
TTX
36
TTXREQ
35
SC
R
ESET/R
T
C
34
R
SET
32
DAC A
31
DAC B
30
VAA
27
DAC D
28
VAA
29
GND
33
VREF
26
DAC C
25
COMP
24
SDATA
23 SCLOCK
2
P5
3
P6
4
P7
7
P10
6
P9
5
P8
1
VAA
8
P11
9
P12
10
GND
11
VAA
12
P13
13
P14
14
P15
15
H
SYN
C
16
FIELD
/VSYN
C
17
BLANK
18
ALS
B
19
GND
20
V
AA
21
GND
22
R
ESET
PIN 1
ADV7170/ADV7171
MQFP/TQFP
TOP VIEW
(Not to Scale)
00221-005
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Description
1, 11, 20, 28, 30
VAA
P
Power Supply (3 V to 5 V).
2 to 9, 12 to 14,
38 to 42
P15 to P0
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7 to P0) or 16-Bit YCrCb Pixel Port (P15 to P0).
P0 represents the LSB.
10, 19, 21, 29, 43
GND
G
Ground Pin.
15
HSYNC
I/O
HSYNC (Mode 1 and Mode 2) Control Signal. This pin may be configured to output (master
mode) or accept (slave mode) sync signals.
16
FIELD/VSYNC
I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be
configured to output (master mode) or accept (slave mode) these control signals.
17
BLANK
I/O
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level 0. This
signal is optional.
18
ALSB
I
TTL Address Input. This signal sets up the LSB of the MPU address.
22
RESET
I
The input resets the on-chip timing generator and sets the ADV7170/ADV7171 into default
mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and
S-Video out, and DAC B powered on and DAC D powered off.
23
SCLOCK
I
MPU Port Serial Interface Clock Input.
24
SDATA
I/O
MPU Port Serial Data Input/Output.
25
COMP
O
Compensation Pin. Connect a 0.1 μF capacitor from COMP to VAA. For optimum dynamic
performance in low power mode, the value of the COMP capacitor can be lowered to as low
as 2.2 nF.
26
DAC C
O
RED/S-Video C/V Analog Output.
27
DAC D
O
GREEN/S-Video Y/Y Analog Output.
31
DAC B
O
BLUE/Composite/U Analog Output.
32
DAC A
O
PAL/NTSC Composite Video Output. Full-scale output is 180 IRE (1286 mV) for NTSC and
1300 mV for PAL.
33
VREF
I/O
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
34
RSET
I
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes
of the video signals.
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