參數(shù)資料
型號(hào)： ADV7171KSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/64頁(yè)
文件大小： 0K
描述： IC DAC VIDEO ENC NTSC 44-MQFP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 800
類型： 視頻編碼器
應(yīng)用： 機(jī)頂盒，視頻播放器
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-QFP
供應(yīng)商設(shè)備封裝： 44-MQFP（10x10）
包裝： 帶卷 (TR)
ADV7170/ADV7171
Rev. C | Page 18 of 64
FEATURES
COLOR BAR GENERATION
The ADV7170/ADV7171 can be configured to generate
100/7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars
for PAL. These are enabled by setting MR17 of Mode Register 1
to Logic Level 1.
SQUARE PIXEL MODE
The ADV7170/ADV7171 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of 29.5
MHz is required. The internal timing logic adjusts accordingly
for square pixel mode operation. When the ADV7171 is
configured for PAL square pixel mode, it supports 768 active
pixels per line. NTSC square pixel mode supports 640 active
pixels per line.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
PIXEL TIMING DESCRIPTION
The ADV7170/ADV7171 operate in either 8-bit or 16-bit
YCrCb mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7 to P0 pixel inputs. The inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, and so on. The Y, Cb, and Cr data are input
on a rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7 to P0 pixel inputs
and multiplexed CrCb inputs through the P15 to P8 pixel
inputs. The data is loaded on every second rising edge of
CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1,
Y2, and so on.
SUBCARRIER RESET
Together with the SCRESET/RTC pin and Bit MR22 and
Bit MR21 of Mode Register 2, the ADV7170/ADV7171
can be used in subcarrier reset mode. The subcarrier resets
to Field 0 at the start of the following field when a low-to-high
transition occurs on this input pin.
REAL-TIME CONTROL
Together with the SCRESET/RTC pin and Bit MR22 and
Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used to lock to an external video source. The real-time control
mode allows the ADV7170/ADV7171 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7185 video
decoder, shown in Figure 19), the part automatically changes to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide, and the subcarrier is
contained in Bit 0 to Bit 21. Each bit is 2 clock cycles long.
00Hex should be written into all four subcarrier frequency
registers when using this mode.
VIDEO TIMING DESCRIPTION
The ADV7170/ADV7171 are intended to interface to off-the-
shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7170/ADV7171 accept 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port, and they have several video timing modes
of operation that allow them to be configured as either system
master video timing generators or as slaves to the system video
timing generator. The ADV7170/ADV7171 generate all of the
required horizontal and vertical timing periods and levels for
the analog video outputs.
The ADV7170/ADV7171 calculate the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration
and equalization pulses are inserted where required.
In addition, the ADV7170/ADV7171 support a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock of
29.5 MHz for PAL. The internal horizontal line counters place the
various video waveform sections in the correct location for the new
clock frequencies.
The ADV7170/ADV7171 have four distinct master and four
distinct slave timing configurations. Timing Control is established
with the bidirectional SYNC, BLANK, and FIELD/VSYNC pins.
Timing Mode Register 1 can also be used to vary the timing pulse
widths where they occur in relation to each other.
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