參數(shù)資料
型號(hào)： ADUC7039BCP6Z-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 58/92頁(yè)
文件大?。?/td> 0K
描述： IC MCU ARM7 BATT SENSER 32LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 6
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7039
Rev. D | Page 61 of 92
TIMERS
The ADuC7039 features three general-purpose timers/counters:
Timer0, or general-purpose timer
Timer1, or wake-up timer
Timer2, or watchdog timer
Timers are started by writing data to the control register of the
corresponding timer (TxCON). The counting mode and speed
depend on the configuration chosen in TxCON.
In normal mode, an IRQ is generated each time the value of
the counter reaches 0 when counting down, or each time the
counter value reaches full scale when counting up. An IRQ
can be cleared by writing any value to clear the register of
that particular timer (TxCLRI).
The three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, starting with the value in the TxLD
register, the counter decrements/increments from the maximum/
minimum value until zero/full scale and starts again at the
maximum/minimum value. This means that, in free-running
mode, TxVAL is not re-loaded when the relevant interrupt bit is
set but the count simply rolls over as the counter underflows or
overflows.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale
starts again from this value. This means when the relevant
interrupt bit is set, TxVAL is re-loaded with TxLD and counting
starts again from this value.
Loading the TxLD register with zero, is not recommended. The
value of a counter can be read at any time by accessing its value
register (TxVAL).
SYNCHRONIZATION OF TIMERS ACROSS
ASYNCHRONOUS CLOCK DOMAINS
Figure 23 shows the interface between the user’s timer MMRs
and the core timer blocks. User code can access all timer MMRs
directly, including TxLD, TxVAL, TxCON, and TxCLRI. Data
must then transfer from these MMRs to the core timers (T0, T1,
and T2) within the timer subsystem. Theses core timers are
buffered from the user’s MMR interface by the synchronization
(SYNC) block. The main purpose of the SYNC block is to
provide a method that ensures data and other required control
signals and can cross asynchronous clock domains correctly. An
example of asynchronous clock domains is the MCU running
on 10 MHz core clock and Timer1 running on the low power
oscillator of 32 KHz.
Figure 23. Timer Block Diagram
08
46
3-
03
3
USEER
MMR
INERFACE
T0 REG
T1 REG
T2 REG
ARM7TDMI
AMBA
CORE
CLOCK
LOW
POWER
OSCILLATOR
T0
SYNC
T1
SYNC
T2
SYNC
T0
T1
T2
0
1
2
T2IRQ
T1IRQ
T0IRQ
WDRST
AMBA
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