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| 型號： | ADUC7039BCP6Z-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU ARM7 BATT SENSER 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI |
| 外圍設(shè)備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 6 |
| 程序存儲(chǔ)器容量： | 64KB（32K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 115°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7039
Data Sheet
Rev. D | Page 24 of 92
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
Initial page erase sequence.
Read/verify sequence.
Byte program sequence.
Second read/verify sequence.
In reliability qualification, every half-word (16-bit wide) loca-
tion of the three pages (top, middle, and bottom) in the Flash/EE
memory is cycled 10,000 times from 0x0000 to 0xFFFF. As
indicated in Table 1, the Flash/EE memory endurance qualifi-
cation of the part is carried out in accordance with the JEDEC
Retention Lifetime Specification A117. The results allow the
specification of a minimum endurance figure over supply and
temperature of 10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. The part is qualified in
accordance with the formal JEDEC Retention Lifetime Specifi-
cation A117 at a specific junction temperature (TJ = 85°C) as
indicated in Table 1. This means that the Flash/EE memory
is guaranteed to retain its data for its fully specified retention
lifetime every time the Flash/EE memory is reprogrammed.
Also, note that retention lifetime, based on an activation energy
Figure 8. Flash/EE Memory Data Retention
ADuC7039 KERNEL
The ADuC7039 features an on-chip kernel resident in the
top 2 kB of the Flash/EE code space. After any reset event,
this kernel calculates its own checksum and compares it to the
checksum programmed during production test, to ensure that
the kernel does not contain any error. If an error occurs, the
SYSCHK register contains its default value and user mode is
entered. In normal circumstances, the checksum is written to
the SYSCHK MMR.
System Kernel Checksum
Name:
SYSCHK
Address:
0xFFFF0244
Default Value: 0x00000000 (updated by kernel at power-on)
Access:
Read/write
Function:
At power-on, this 32-bit register holds the
kernel checksum.
The kernel then copies the factory calibrated data from the
manufacturing data space into the various on-chip peripherals.
The peripherals calibrated by the kernel are as follows:
Precision oscillator
Low power oscillator
REG_AVDD/REG_DVDD
Voltage reference
Current ADC (offset and gain)
Voltage/temperature ADC (offset and gain)
Processor registers and user registers that can be modified
by the kernel and differ from their POR default values are as
follows:
R0 to R15
GP0CON
SYSCHK
FEEADR/FEEDAT/FEECON/FEESIG
HVDAT/HVCON
HVCFG
T2LD
The ADuC7039 also features an on-chip LIN downloader.
A flow chart of the execution of the kernel is shown in Figure 9.
The current revision of the kernel can be derived from R5, as
described in Table 66.
After any reset, the watchdog timer is disabled once the kernel
code is exited. For the duration of the kernel execution, the
watchdog timer is active with a timeout period of 500 ms. This
ensures that if an error occurs in the kernel, the ADuC7039
automatically resets. If LIN download mode is entered, the
watchdog is periodically refreshed.
0
150
300
450
600
30
40
55
70
85
100
125
135
150
RE
T
E
NT
IO
N
(
Y
ears)
JUNCTION TEMPERATURE (°C)
08463-
009
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