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參數(shù)資料
| 型號： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 75/128頁 |
| 文件大小： | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲器容量： | 96KB（48K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標準包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 50 of 128
4
Current Channel ADC Comparator Threshold
This bit is only valid if the Current Channel ADC comparator is enabled via the ADCCFG MMR. This bit is set by hardware if the
absolute value of the I-ADC conversion result exceeds the value written in the ADC0TH MMR. If the ADC threshold counter is
used (ADC0TCL), this bit is only set once the specified number of I-ADC conversions equals the value in the ADC0THV MMR.
3
Current Channel ADC Over-Range Bit
If the Over-Range Detect function is enabled via the ADCCFG MMR, this bit is set by hardware if the I-ADC input is grossly
(>30% approx.) over-ranged. This bit is updated every 125usecs. Once set, t
his bit can only be cleared by software when
ADCCFG[2] is cleared to disable the function, or the ADC gain is changed via the ADC0CON MMR.
2
Temperature Conversion Result Ready Bit
If the Temperature Channel ADC is enabled, this bit is set by hardware as soon as a valid temperature conversion result is
written in the temperature data register (ADC2DAT MMR)
This bit is cleared by reading either ADC2DAT or ADC0DAT.
1
Voltage Conversion Result Ready Bit
If the Voltage Channel ADC is enabled, this bit is set by hardware as soon as a valid voltage conversion result is written in the
voltage data register (ADC1DAT MMR)
This bit is cleared by reading either ADC1DAT or ADC0DAT.
0
Current Conversion Result Ready Bit
If the Current Channel ADC is enabled, this bit is set by hardware as soon as a valid current conversion result is written in the
current data register (ADC0DAT MMR)
This bit is cleared by reading ADC0DAT.
NOTES
1.
All bits defined in the top 8 MSBs (bits 8–15) of the MMR are used as flags only and will not generate interrupts
2.
All bits defined in the lower 8 LSBs (bits 0-7) of this MMR are logic OR’ed to produce a single ADC interrupt to the MCU core.
3.
In response to an ADC interrupt, user code should interrogate the ADCSTA MMR to determine the source of the interrupt.
4.
Each ADC interrupt source can be individually masked via the ADCMSKI MMR described below
5.
All ADC Result Ready bits are cleared by a read of the ADC0DAT MMR. If the Current Channel ADC is not enabled, all ADC
Result Ready bits are cleared by a read of the ADC1DAT or ADC2DAT MMRs.
6.
To ensure that I-ADC, V-ADC and T-ADC conversion data are synchronous, user code should first read the
ADC2DAT/ADC1DAT MMRs and then ADC0DAT MMR.
7.
New ADC conversion results will not be written to the ADCxDAT MMRs unless the respective ADC Result Ready bits are first
cleared. The only exception to this rule is data conversion result updates when the ARM core is powered down. In this
modes ADCxDAT registers will always contain the most recent ADC conversion result even though the Ready bits have not
been cleared.
ADC Interrupt Mask Register :
Name :
ADCMSKI
Address :
0xFFFF0504
Default Value :
0x00
Access :
Read/Write
Function :
This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the
same as the lower 8-bits in the ADCSTA MMR. If a bit is set by user code to a ‘1’, the respective interrupt is enabled.
By default all bits are ‘0’ meaning all ADC interrupt sources are disabled.
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