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參數(shù)資料
| 型號(hào)： | ADUC7032BSTZ-8V-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 49/128頁(yè) |
| 文件大小： | 0K |
| 描述： | IC BATTERY SENSOR PREC 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 20.48MHz |
| 連通性： | LIN，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 9 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1.5K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 3.5 V ~ 18 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7032BSTZ-8V-RLDKR |
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Preliminary Technical Data
ADuC7032
Rev. PrD | Page 27 of 128
EmbeddedICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers which allow
non intrusive user code debugging. These registers are
controlled through the JTAG test port.
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers may be interrogated, as well as the Flash/EE,
the SRAM and the Memory Mapped Registers.
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are:
- Normal interrupt or IRQ. It is provided to service general-
purpose interrupt handling of internal and external events
- Fast interrupt or FIQ. It is provided to service data transfer or
communication channel with low latency. FIQ has priority
over IRQ
- Memory abort (Prefetch and Data)
- Attempted execution of an undefined instruction
- Software interrupt (SWI) instruction which can be used to
make a call to an operating system.
Typically the programmer will define interrupts as IRQ but for
higher priority interrupts, the programmer can define
interrupts as of type FIQ.
The priority of the above exceptions and vector address are as
follows:
1.
Hardware Reset
0x00
2.
Memory Abort ( Data )
0x10
3.
FIQ
0x1C
4.
IRQ
0x18
5.
Memory Abort ( Prefetch )
0x0C
6.
Software Interrupt and
0x08
Undefined Instruction
0x04
Note:
A Software interrupt and an Undefined Instruction
exception have the same priority and are mutually exclusive.
NOTE:
The above list are located from 0x00 -0x1C, with a
reserved location at 0x14. This location is required to be written
with either 0x27011970 or the checksum of Page Zero,
excluding location 0x14. If this is not done, user code will not
be executed and LIN download mode will be entered. For more
information please refer to the ADuC7032 LIN download
Technote.
ARM Registers
The ARM7TDMI has 16 standard registers. R0-R12 are used for
data manipulation, R13 is the stack pointer, R14 is the link
register and R15 is the program counter which indicates the
instruction currently being executed. The link register contains
the address from which the user has branched, if the branch and
link command was used, or the command during which an
exception occurred.
The stack pointer contains the current location of the stack. As
a general rule of thumb on an ARM7TDMI, the stack starts at
the top of the available RAM area, and descends, using the area
as required. A separate stack is defined for each of the
exceptions. The size of each stack is user configurable and is
dependent on the target application. On the ADuC7032 the
stack begins at 0x000417FC and descends.
Whilst programming using high level languages, such as C, it
may be possible to ensure that the stack does not overflow. This
is dependent on the compiler used.
When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented in
Figure 9. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of non-critical registers, the interrupt may be
processed without the need to save or restore these registers,
which reduces the response time of the interrupt handling
process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents available from ARM Ltd.:
- DDI0029G, ARM7TDMI Technical Reference Manual.
- DDI0100E, ARM Architecture Reference Manual..
05994-
008
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_UND
SPSR_IRQ
SPSR_ABT
SPSR_SVC
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_UND
R14_UND
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R13_IRQ
R14_IRQ
R13_ABT
R14_ABT
R13_SVC
R14_SVC
SPSR_FIQ
CPSR
USER MODE
FIQ
MODE
SVC
MODE
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
Figure 9: ADuC7032 Register Organization
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