- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374037 > ADSP-BF561 (Analog Devices, Inc.) Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 PDF資料下載
參數(shù)資料
| 型號： | ADSP-BF561 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| 中文描述： | 嵌入式Blackfin處理器的對稱多處理器 |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 508K |
| 代理商： | ADSP-BF561 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 7 of 52
|
April 2004
Event Control
The ADSP-BF561 provides the user with a very flexible mecha-
nism to control the processing of events. In the CEC, three
registers are used to coordinate and control events. Each of the
registers, as follows, is 16-bits wide, while each bit represents a
particular event class:
CEC Interrupt Latch Register (ILAT) – The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
may be written only when its corresponding IMASK bit is
cleared.
CEC Interrupt Mask Register (IMASK) – The IMASK reg-
ister controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event
thereby preventing the processor from servicing the event
even though the event may be latched in the ILAT register.
This register may be read from or written to while in super-
visor mode. (Note that general-purpose interrupts can be
globally enabled and disabled with the STI and CLI instruc-
tions, respectively.)
CEC Interrupt Pending Register (IPEND) – The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
Table 2. Peripheral Interrupt Source Reset State
Peripheral Interrupt Source
PLL wakeup
DMA1 Error
DMA2 Error
IMDMA Error
PPI1 Error
PPI2 Error
SPORT0 Error
SPORT1 Error
SPI Error
UART Error
Reserved
DMA1 0 interrupt
DMA1 1 interrupt
DMA1 2 interrupt
DMA1 3 interrupt
DMA1 4 interrupt
DMA1 5 interrupt
DMA1 6 interrupt
DMA1 7 interrupt
DMA1 8 interrupt
DMA1 9 interrupt
DMA1 10 interrupt
DMA1 11 interrupt
DMA2 0 interrupt
DMA2 1 interrupt
DMA2 2 interrupt
DMA2 3 interrupt
DMA2 4 interrupt
DMA2 5 interrupt
DMA2 6 interrupt
DMA2 7 interrupt
DMA2 8 interrupt
DMA2 9 interrupt
DMA2 10 interrupt
DMA2 11 interrupt
Timer0 interrupt
Timer1 interrupt
Timer2 interrupt
Timer3 interrupt
Timer4 interrupt
Timer5 interrupt
Timer6 interrupt
Timer7 interrupt
Timer8 interrupt
Timer9 interrupt
Timer10 interrupt
Chan
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
IVG
2
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG07
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG08
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG09
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
Timer11 interrupt
FIO0 interrupt A
FIO0 interrupt B
FIO1 interrupt A
FIO1 interrupt B
FIO2 interrupt A
FIO2 interrupt B
DMA1 write/read 0 interrupt
DMA1 write/read1 interrupt
DMA2 write/read 0 interrupt
DMA2 write/read 1 interrupt
IMDMA write/read 0 interrupt
IMDMA write/read 1 interrupt
Watchdog Timer
Reserved
Reserved
Supplemental 0
Supplemental 1
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG08
IVG08
IVG09
IVG09
IVG12
IVG12
IVG13
IVG07
IVG07
IVG07
IVG07
1
Peripheral Interrupt Channel Number
2
Default User IVG Interrupt
Table 2. Peripheral Interrupt Source Reset State (Continued)
Peripheral Interrupt Source
Chan
1
IVG
2
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-BF561SBB500 | Blackfin Embedded Symmetric Multi-Processor |
| ADSP21020 | 32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP-21020BG-100 | 32/40-Bit IEEE Floating-Point DSP Microprocessor |
| ADSP2184 | 16 A SPDT MINIATURE POWER RELAY |
| ADSP2185 | DSP Microcomputer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| adsp-bf5615bbz600 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ADSP-BF561KBCZ-600 | 制造商:Analog Devices 功能描述: |
| ADSP-BF561SBB500 | 功能描述:IC PROCESSOR 500MHZ 297PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF561SBB600 | 功能描述:IC DSP 32BIT 600MHZ 297-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF561SBB600 | 制造商:Analog Devices 功能描述:IC MULTIPROCESSOR |
發(fā)布緊急采購，3分鐘左右您將得到回復。