參數(shù)資料
型號: ADSP-BF561
廠商: Analog Devices, Inc.
元件分類: 通用總線功能
英文描述: Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70
中文描述: 嵌入式Blackfin處理器的對稱多處理器
文件頁數(shù): 3/52頁
文件大小: 508K
代理商: ADSP-BF561
ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 3 of 52
|
April 2004
GENERAL DESCRIPTION
The ADSP-BF561 processor is a high-performance member of
the Blackfin family of products targeting a variety of multimedia
and telecommunications applications. At the heart of this device
are two independent Analog Devices Blackfin processors. These
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantage of a clean, orthogonal RISC-
like microprocessor instruction set, and single-instruction, mul-
tiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture. The ADSP-BF561 device integrates
a general purpose set of digital imaging peripherals creating a
complete system on-chip solution for digital imaging and multi-
media applications.
The ADSP-BF561 processor has 328 KBytes of on-chip mem-
ory. Each Blackfin core includes:
16K Bytes of Instruction SRAM/Cache
16K Bytes of Instruction SRAM
32K Bytes of Data SRAM/Cache
32K Bytes of Data SRAM
4K Bytes of Scratchpad SRAM
Additional on-chip memory peripherals include:
128 KBytes of Low Latency On-chip SRAM
Four Channel Internal Memory DMA Controller
External Memory controller with glueless support for
SDRAM, SRAM, and Flash
PORTABLE LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance for embedded signal processing applications.
Blackfin processors are designed in a low power and low voltage
design methodology and feature Dynamic Power Management.
Dynamic Power Management is the ability to vary both the volt-
age and frequency of operation to significantly lower the overall
power dissipation. This translates into an exponential reduction
in power dissipation providing longer battery life to portable
applications.
BLACKFIN PROCESSOR CORE
As shown in
Figure 2
, each Blackfin core contains two multi-
plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,
and a single shifter. The computational units process 8-bit, 16-
bit, or 32-bit data from the register file.
Figure 2. Blackfin Processor Core
SP
FP
P5
P4
P3
P2
P1
P0
SEQUENCER
ALIGN
DECODE
LOOPBUFFER
DAG0
DAG1
16
16
8
8
8
8
40
40
A0
A1
BARREL
SHIFTER
DATA ARITHMETIC UNIT
CONTROL
UNIT
ADDRESS ARITHMETIC UNIT
R7
R6
R5
R4
R3
R2
R1
R0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
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ADSP-BF561KBCZ-600 制造商:Analog Devices 功能描述:
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ADSP-BF561SBB600 制造商:Analog Devices 功能描述:IC MULTIPROCESSOR