參數資料
型號: ADSP-BF561
廠商: Analog Devices, Inc.
元件分類: 通用總線功能
英文描述: Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70
中文描述: 嵌入式Blackfin處理器的對稱多處理器
文件頁數: 18/52頁
文件大小: 508K
代理商: ADSP-BF561
Rev. PrC
|
Page 18 of 52
|
April 2004
ADSP-BF561
Preliminary Technical Data
PF/TIMER
PF15/EXT CLK
I/O
1
Programmable Flag
/ external timer clock input
Programmable Flag
C
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
software configurable,
no pull-up/down necessary
needs to be at a level or
clocking
none
always active if core power on
none
pull-up or pull-down required
PF14
I/O
1
C
PF13
I/O
1
Programmable Flag
C
PF12
I/O
1
Programmable Flag
C
PF11
I/O
1
Programmable Flag
C
PF10
I/O
1
Programmable Flag
C
PF9
I/O
1
Programmable Flag
C
PF8
I/O
1
Programmable Flag
C
PF7/SPISEL7/
TMR7
PF6/SPISEL6/
TMR6
PF5/SPISEL5/
TMR5
PF4/SPISEL4/
TMR4
PF3/SPISEL3/
TMR3
PF2/SPISEL2/
TMR2
PF1/SPISEL1/
TMR1
PF0/SPISS/
TMR0
CLKIN
I/O
1
Programmable Flag / SPI Select
/ Timer
Programmable Flag / SPI Select
/ Timer
Programmable Flag / SPI Select
/ Timer
Programmable Flag / SPI Select
/ Timer
Programmable Flag / SPI Select
/ Timer
Programmable Flag / SPI Select
/ Timer
Programmable Flag / SPI Select
/ Timer
Programmable Flag / Slave SPI Select
/ Timer
Clock input
C
I/O
1
C
I/O
1
C
I/O
1
C
I/O
1
C
I/O
1
C
I/O
1
C
I/O
1
C
Clock
Generator
I
1
-
XTAL
RESET
SLEEP
BMODE[1:0]
O
I
O
I
1
1
1
2
Crystal connection
Chip reset signal
Sleep
Dedicated Mode Pin, Configures
the boot mode that is employed
following a hardware reset or
software reset
PLL BYPASS control
Non Maskable interrupt Core A
-
-
C
-
Mode
Controls
BYPASS
NMI0
I
I
1
1
-
-
pull-up or pull-down required
pull-down required if function not
used
pull-down required if function not
used
N/A
NMI1
I
1
Non Maskable interrupt Core B
-
Regulator
VROUT1-0
O
2
Regulation output
-
Table 8. Pin Descriptions (Continued)
Block
Pin Name
Type Signals Function
Driver
Type
Pull-up/down requirement
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