參數(shù)資料
型號: AD9995
廠商: Analog Devices, Inc.
英文描述: 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
中文描述: 12位CCD信號處理器與精密計時⑩發(fā)生器
文件頁數(shù): 43/60頁
文件大小: 1593K
代理商: AD9995
AD9995
–43–
COMPLETE LISTING FOR REGISTER BANK 2
All V-pattern group and V-sequence registers are SCP updated, and all Field registers are VD updated.
All address and default values are in hexadecimal.
Table XXVI. V-Pattern Group 0 (VPAT0) Register Map
Data Bit Default
Address Content
00
Value
0
0
0
Register Name
VPOL_0
UNUSED
VPATLEN_0
Description
VPAT0 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Unused.
Total Length of VPAT0. Note: If using VPAT0 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
V1 Toggle Position 1
V1 Toggle Position 2
V1 Toggle Position 3
V2 Toggle Position 1
V2 Toggle Position 2
V2 Toggle Position 3
V3 Toggle Position 1
V3 Toggle Position 2
V3 Toggle Position 3
V4 Toggle Position 1
V4 Toggle Position 2
V4 Toggle Position 3
V5 Toggle Position 1
V5 Toggle Position 2
V5 Toggle Position 3
V6 Toggle Position 1
V6 Toggle Position 2
V6 Toggle Position 3
V1–V6 Freeze Position 1
V1–V6 Resume Position 1
V1–V6 Freeze Position 2
V1–V6 Resume Position 2
[5:0]
[11:6]
[23:12]
01
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V1TOG1_0
V1TOG2_0
V1TOG3_0
V2TOG1_0
V2TOG2_0
V2TOG3_0
V3TOG1_0
V3TOG2_0
V3TOG3_0
V4TOG1_0
V4TOG2_0
V4TOG3_0
V5TOG1_0
V5TOG2_0
V5TOG3_0
V6TOG1_0
V6TOG2_0
V6TOG3_0
FREEZE1_0
RESUME1_0
FREEZE2_0
RESUME2_0
02
03
04
05
06
07
08
09
0A
0B
Table XXVII. V-Pattern Group 1 (VPAT1) Register Map
Data Bit Default
Address Content
0C
Value
0
0
0
Register Name
VPOL_1
UNUSED
VPATLEN_1
Description
VPAT1 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Unused.
Total Length of VPAT1. Note: If using VPAT1 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
V1 Toggle Position 1
V1 Toggle Position 2
V1 Toggle Position 3
V2 Toggle Position 1
V2 Toggle Position 2
V2 Toggle Position 3
V3 Toggle Position 1
V3 Toggle Position 2
V3 Toggle Position 3
V4 Toggle Position 1
V4 Toggle Position 2
V4 Toggle Position 3
[5:0]
[11:6]
[23:12]
0D
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
0
0
0
0
0
0
0
0
0
0
0
0
V1TOG1_1
V1TOG2_1
V1TOG3_1
V2TOG1_1
V2TOG2_1
V2TOG3_1
V3TOG1_1
V3TOG2_1
V3TOG3_1
V4TOG1_1
V4TOG2_1
V4TOG3_1
0E
0F
10
11
12
REV. 0
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