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參數(shù)資料
| 型號： | AD9995 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| 中文描述： | 12位CCD信號處理器與精密計時⑩發(fā)生器 |
| 文件頁數(shù)： | 22/60頁 |
| 文件大?。?/td> | 1593K |
| 代理商： | AD9995 |
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AD9995
–22–
The example shown in Figure 22 illustrates this operation. The
first toggle position is 2, and the second toggle position is 9. In
non-Multiplier mode, this causes the V-sequence to toggle at
pixel 2 and then pixel 9 within a single HD line. However, toggle
positions are now multiplied by the VTPLEN = 4, so the first
toggle occurs at pixel count 8 and the second toggle occurs at
pixel count 36. Sweep mode has also been enabled to allow the
toggle positions to cross the HD line boundaries.
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gates (VSG) are used
to transfer the pixel charges from the light-sensitive image area
into light-shielded vertical registers. From the light-shield verti-
cal registers, the image is then read out line-by-line by using the
vertical transfer pulses V1–V6 in conjunction with the high speed
horizontal clocks.
Table IX contains the summary of the VSG pattern registers. The
AD9995 has five VSG outputs, VSG1–VSG5. Each of the out-
puts can be assigned to one of four programmed patterns by using
the SGPATSEL registers. Each pattern is generated in a similar
manner as the V-pattern groups, with a programmable start polar-
ity (SGPOL), first toggle position (SGTOG1), and second toggle
position (SGTOG2). The active line where the VSG1–VSG5
pulses occur is programmable using the SGLINE1 and SGLINE2
registers. Additionally, any of the VSG1–VSG5 pulses may be
individually disabled by using the SGMASK register. The individ-
ual masking allows all of the SG patterns to be preprogrammed,
and the appropriate pulses for the different fields can be separately
enabled. For maximum flexibility, the SGPATSEL, SGMASK,
and SGLINE registers are separately programmable for each field.
More detail is given in the Complete Field section.
V1–V6
HD
VPATLEN
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:
1. START POLARITY (ABOVE: STARTPOL = 0)
2. FIRST, SECOND, AND THIRD TOGGLE POSITIONS (ABOVE: VTOG1 = 2, VTOG2 = 9)
3. LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4). THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4. TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG
VPATLEN)
5. IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
PIXEL
NUMBER
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
5
5
4
1
2
4
2
Figure 22. Example of Multiplier Region for Wide Vertical Pulse Timing
Table IX. VSG Pattern Registers (also see Field Registers in Table VII)
Length
Range
1b
High/Low
12b
0–4095 Pixel Location
12b
0–4095 Pixel Location
Register
SGPOL
SGTOG1
SGTOG2
Description
Sensor Gate Starting Polarity for SG Pattern 0–3
First Toggle Position for SG Pattern 0–3
Second Toggle Position for SG Pattern 0–3
VD
HD
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1. START POLARITY OF PULSE
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION
4. ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN)
VSG PATTERNS
4
1
2
3
Figure 23. Vertical Sensor Gate Pulse Placement
REV. 0
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| AD9995KCPZRL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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