參數(shù)資料
型號: AD9991KCP
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC56
封裝: 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁數(shù): 50/60頁
文件大小: 826K
代理商: AD9991KCP
AD9991
–50–
Table XXXVIII. V-Sequence 1 (VSEQ1) Register Map
Data Bit Default
Address Content Value Register Name Description
88 [1:0] 0 HBLKMASK_1 Masking Polarity during HBLK. H1 [0]. H3 [1].
[2] 0 CLPOBPOL_1 CLPOB Start Polarity
[3] 0 PBLKPOL_1 PBLK Start Polarity
[7:4] 0 VPATSEL_1 Selected V-Pattern Group for V-Sequence 1
[9:8] 0 VMASK_1 Enable Masking of V-) Outputs (Specified by Freeze/Resume Registers)
[11:10] 0 HBLKALT_1 Enable HBLK Alternation
[23:12] 0 UNUSED Unused
89 [11:0] 0 VPATREPO_1 Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12] 0 VPATREPE_1 Number of Selected V-Pattern Group Repetitions for Even Lines
8A [11:0] 0 VPATSTART_1 Start Position in the Line for the Selected V-Pattern Group
[23:12] 0 HDLEN_1 HD Line Length (Number of Pixels) for V-Sequence 1
8B [11:0] 0 PBLKTOG1_1 PBLK Toggle Position 1 for V-Sequence 1
[23:12] 0 PBLKTOG2_1 PBLK Toggle Position 2 for V-Sequence 1
8C [11:0] 0 HBLKTOG1_1 HBLK Toggle Position 1 for V-Sequence 1
[23:12] 0 HBLKTOG2_1 HBLK Toggle Position 2 for V-Sequence 1
8D [11:0] 0 HBLKTOG3_1 HBLK Toggle Position 3 for V-Sequence 1
[23:12] 0 HBLKTOG4_1 HBLK Toggle Position 4 for V-Sequence 1
8E [11:0] 0 HBLKTOG5_1 HBLK Toggle Position 5 for V-Sequence 1
[23:12] 0 HBLKTOG6_1 HBLK Toggle Position 6 for V-Sequence 1
8F [11:0] 0 CLPOBTOG1_1 CLPOB Toggle Position 1 for V-Sequence 1
[23:12] 0 CLPOBTOG2_1 CLPOB Toggle Position 2 for V-Sequence 1
Table XXXIX. V-Sequence 2 (VSEQ2) Register Map
Data Bit Default
Address Content Value Register Name Description
90 [1:0] 0 HBLKMASK_2 Masking Polarity during HBLK. H1 [0]. H3 [1].
[2] 0 CLPOBPOL_2 CLPOB Start Polarity
[3] 0 PBLKPOL_2 PBLK Start Polarity
[7:4] 0 VPATSEL_2 Selected V-Pattern Group for V-Sequence 2
[9:8] 0 VMASK_2 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers)
[11:10] 0 HBLKALT_2 Enable HBLK Alternation
[23:12] 0 UNUSED Unused
91 [11:0] 0 VPATREPO_2 Number of Selected V-Pattern Group Repetitions for Odd Lines
[23:12] 0 VPATREPE_2 Number of Selected V-Pattern Group Repetitions for Even Lines
92 [11:0] 0 VPATSTART_2 Start Position in the Line for the Selected V-Pattern Group
[23:12] 0 HDLEN_2 HD Line Length (Number of Pixels) for V-Sequence 2
93 [11:0] 0 PBLKTOG1_2 PBLK Toggle Position 1 for V-Sequence 2
[23:12] 0 PBLKTOG2_2 PBLK Toggle Position 2 for V-Sequence 2
94 [11:0] 0 HBLKTOG1_2 HBLK Toggle Position 1 for V-Sequence 2
[23:12] 0 HBLKTOG2_2 HBLK Toggle Position 2 for V-Sequence 2
95 [11:0] 0 HBLKTOG3_2 HBLK Toggle Position 3 for V-Sequence 2
[23:12] 0 HBLKTOG4_2 HBLK Toggle Position 4 for V-Sequence 2
96 [11:0] 0 HBLKTOG5_2 HBLK Toggle Position 5 for V-Sequence 2
[23:12] 0 HBLKTOG6_2 HBLK Toggle Position 6 for V-Sequence 2
97 [11:0] 0 CLPOBTOG1_2 CLPOB Toggle Position 1 for V-Sequence 2
[23:12] 0 CLPOBTOG2_2 CLPOB Toggle Position 2 for V-Sequence 2
REV. 0
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